The sleep transistor design style is expected to cut leakage current from tenfold to one-hundredfold with the help of computer-aided design (CAD) tools that have yet to be developed. Intel expects to employ the sleep circuit techniques in microprocessors based on future 0.10-micron or 0.065-micron process rules, said Desmond Kirkpatrick, a CAD researcher with Intel.

The sleep transistor technique is similar to clock gating, which disables the clocks in inactive areas of a chip to reduce power consumption. "Instead of gating the clock, you're gating the power," Kirkpatrick said in an interview here at the 39th Design Automation Conference. "It's clear from a technology viewpoint that it works, but implementing it depends on EDA."

Kirkpatrick disclosed Intel's low-power circuit plans during a panel discussion on the EDA tools that will be needed to overcome future silicon engineering challenges.

To implement sleep transistors, Intel's circuit designers will need software tools that can partition specific areas of a chip that would use the low-power circuits and determine their size. Compared to other circuit types, sleep transistor circuits will take up more area and are more prone to delay than other types of digital circuits, Intel said.

"Power is such a concern that we are willing to pay a little for that," Kirkpatrick said.

Intel could develop the needed EDA tools in-house, but plans to seek the help of universities and leading-edge designers, Kirkpatrick said. The sleep transistor technique itself is based on research by Kaushik Roy of Purdue University.

Leakage current, a phenomenon that causes transistors to consume power during their off state, has emerged as one of the top concerns for high-performance circuit design, particularly at the current 0.13-micron process node. Processor designers commonly rely on lower transistor threshold voltages to boost performance as power supply voltages scale down, but leakage is growing exponentially as a result of this practice, and increases with every turn of the process technology crank.

Leakage current especially nettlesome because only a portion of a microprocessor's circuitry — about 10 percent, Kirkpatrick said — is active during typical operation. And the problem will only intensify as future processors employ a higher number of transistors which are getting more leaky.

Kirkpatrick said leakage current can rise by a factor of two to three for each process generation. "The next generation 0.10 and 0.065 micron looks horrible from a leakage point of view. We almost have to employ sleep transistors at 0.065," he said.

Along with power density and power delivery, leakage current is considered one of the biggest barriers to boosting performance and has become a top priority for Intel's circuit, process and architectural design teams.