The Millipede chip uses silicon micromachining techniques to precisely move a silicon substrate coated with a thin-film polymer beneath an array of 1,024 parallel activated 20-nanometer read/write heads, which were also etched from silicon.

While other memory technologies are reaching the end of their usefulness, IBM Nobel laureate Gerd Beinnig of the Millipede project said nanotechnology is in its infancy, and is good for another "thousandfold increase in data-storage density," which would lead to petabit-sized devices.

"We believe that the Millipede device is a good match for mobile devices like cell phones," said Peter Vettiger, Millipede project leader with IBM Research. "Someday our prototypes may lead to replacement chips you can plug into the same sockets as current flash memory chips, but with incredible storage capacity and only about 100 milliwatts power consumption."

Stressing that the Millipede is a prototype, Vettiger said it will be two years before he can refine the chip to a point where it could even be considered for manufacturing. IBM stated its commitment to nanotechnology in 2000, and said memory was the main strategic goal of its research.

The current Millipede chip uses microelectromechanical systems to physically locate and melt holes in a soft polymer atop a movable silicon substrate. Bit locations are addressed by moving the substrate under the desired read/write head, which is then heated. Static tension causes the head to melt the polymer, making a hole, which can be read later by the same head when it is not heated. Since the polymer is not destroyed, but only displaced, erasure is accomplished by using the head to melt the displaced polymer until it flows back into the hole.

"Erasure can be done on a per bit basis, but since it takes more energy, mobile users will have the option of just marking files for erasure, and delaying the actual erasing operation until, say, the handset is put into its charger at night," said Vettiger.

The terabit densities displayed by IBM's Millipede chip, currently using 1,024 tips or heads in a 3-mm square area, will be increased to 4,096 tips in a 7-mm square area by early next year, according to Vettiger. Capacities could eventually reach 15 gigabytes per chip, more than a tenfold increase over current predictions for flash memory capacities, Vettiger said.