SAN JOSE, Calif. -- PDF Solutions Inc. here today announced its latest software to boost chip yields in semiconductor production.
The Yield Ramp Simulator version 3.0, to be released in August, is a yield modeling and analysis software tool that evaluates the impact of specific IC design attributes in chip manufacturing.
Version 3.0 offers an order of magnitude throughput improvement over previous offering. The latest version also provides a more flexible design attribute extraction engine, which enables accurate analysis of process-design interactions, especially for today's largest, most complex designs.
"YRS version 3.0 provides semiconductor companies with a highly advanced tool to help disaggregate yield loss mechanisms and prioritize yield improvement efforts," said John Kibarian, president of the San Jose-based company.
"PDF's YRS technology is a key component of our capabilities that provide pre-silicon visibility into the process or design features that cause product yield loss. Solving yield issues early by using a virtual environment gives the customer the highest cost-benefit leverage," he explained.
At the core of the YRS yield analysis software are proprietary models of product layout and manufacturing process interactions. These layout-process interaction models support analysis of critical design component yield variation due to optical proximity effects, resist processing models, etch micro loading, pattern dependencies in chemical-mechanical polishing, and particle contamination.
The yield models are calibrated using product-specific data generated by PDF's Characterization Vehicle test chips.
Using YRS software, PDF's customers are able to quickly make informed decisions regarding trade-offs among yield and performance detractors before production starts, based on quantitative simulation of process-design interactions.
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