The microprocessor giant has disclosed some more details about its 90-nm process technology, including that it will be the company's initial deployment of strained silicon and low-k dielectrics in chip production. IBM and other chip makers had indicated that strained silicon would not be used in IC production until the 65-nm node in 2005.

During a briefing with SBN last week, Intel also reiterated plans to develop its 90-nm process exclusively in its 300-mm fabs. And as expected, Intel's first 90-nm product will be a high-speed Pentium 4-based processor comprising 330 million transistors and code-named Prescott. Prescott is due out in the second half of 2003, according to Intel.

Intel spoke of its 90-nm process in March when the Santa Clara-based company announced fully functional, 90-nm SRAM chips with six-transistor memory cells.

The 52-megabit SRAM test chips are being used as a prototyping vehicle for Intel's 90-nm process technology, dubbed P1262. Intel also said its process is a seven-layer-metal, copper-based technology--which will enable chips with 50-nm gate lengths and 1.2-nm thick gate-oxide structures (see March 12 story).

Now Intel has disclosed more details about the process, and claims that it is ahead of other chip makers in a 90-nm race. Fujitsu, IBM, Motorola, TI, TSMC, UMC and others have also separately announced 90-nm processes as well.

"We believe we have the world's most advanced 90-nm process," declared Mark Bohr, an Intel Fellow and director of process architecture and integration for the company. "For example, as far as I know, we are the only company to bring strained silicon at 90-nm," he told SBN in an interview last week.

Surprise step to strained silicon

In fact, Intel's move to strained silicon is somewhat of a surprise. In the past, the company took a wait-and-see approach to this technology, which has been in R&D at IBM and elsewhere for several years, according to analysts.

Now, Intel is embracing strained silicon for powerful reasons. Strained silicon promises to improve electron and hole mobility in a device, which in turns promises faster transistor switching and faster processors. The technology is also said to take advantage of the phenomenon that electrons have higher mobility, when a thin layer of silicon is deposited on top of a thicker, graded layer of material.

Intel claims it has devised a proprietary strained silicon process, which will enable faster processor speeds, Bohr said. "We've been looking at strained silicon for awhile, he said. Strained silicon will improve transistor speeds, which will boost gigahertz performances in microprocessors," he added.

He declined to comment on the exact manufacturing techniques to develop this technology. But the company did say the technology could boost transistor current flows by 10-20%--with little or no cost penalty. The added steps to deploy strained silicon would only increase processing steps by 2%, he said.

Intel is also moving towards a low-k dielectric material at the 90-nm node to boost chip speeds. At the 130-nm node, Intel used traditional fluorine-doped silicate glass (FSG) technology as the insulating material for the copper interconnects.But given the complexities of lower k materials in IC production, Intel's move to use FSG materials at the 130-nm node proved to be the right choice, according to Bohr.

"Half of our total product shipments are based on 0.13-micron technology right now," Bohr said.

In contrast, many other chip makers are struggling to ship product at the 130-nm node, due in part to the complexities of low-k and other factors, he said. "A lot of people talked about going to low-k at 0.13-micron, but they had to back off and go back to FSG," he said.

Bite the bullet

At 90-nm, Intel plans to bite the bullet and deploy a carbon-doped oxide (CDO) material, which reduces the capacitance by 18% compared to FSG. In other words, Intel plans to use a simple, two-layer stack material, with a k value of around 3.0, Bohr said.

It plans to use chemical vapor deposition (CVD) tools as a means to deposit the low-k materials. Sources believe that Intel is leaning towards a CVD-based, low-k solution from ASM International N.V., but the chip giant is also reportedly looking at competitive tools from Applied Materials Inc. and Novellus Systems Inc. Intel declined to comment on its tool vendors.

Intel has made it no secret that it will deploy 248- and 193-nm exposure tools to process its 90-nm chips. The company will reportedly use scanners from ASML Holdings N.V. and Nikon Corp., according to sources.

And as previously reported, Intel is developing its 90-nm technology within its 300-mm D1C development fab in Hillsboro, Ore. In April, Intel also announced plans to "restart" the construction of its 300-mm wafer fab project in Ireland after several delays with the $2.2 billion plant.

The so-called Fab 24 plant in Leixlip is Intel's first high-volume, 90-nm chip fab. Production is expected to start in the first half of 2004 (see April 4 story).