The JEDEC Solid State Technology Association, the semiconductor engineering standards body of the Electronic Industries Alliance, has begun drafting the first DDR-III industry standard even though DDR-II for PC and server main memory has yet to come to market.

Preliminary details indicate DDR-III SDRAM chips will have data transfer rates starting at 800Mbits/s and later increasing to 1.5Gbits/s. DDR-III will also consume much less power than previous memory devices, moving to as little as 1.2 or 1.5V compared with 1.8V for DDR-II and 2.5V for current DDR.

"Each voltage decrease allows a significant power reduction," said Kevin Ryan, director of strategic marketing at Micron Technology Inc., Boise, Idaho.

William Shen, memory applications market manager at Infineon Technologies North America Corp., San Jose, said the density of the first DDR-III SDRAM chip is likely to be 4Gbits.

A final JEDEC standard for DDR-III is expected to be completed by the end of 2005, with sampling starting a year later and production in 2007.

The JEDEX China audience got the first glimpse of next-generation memory chips, a privilege usually reserved for Silicon Valley or other global semiconductor centers. This week's meeting was JEDEC's first offshore conference, reflecting the importance chipmakers are placing on China's burgeoning electronics industry.

"Semiconductor sales in China should remain in double digits for many years, one of the few areas of the world experiencing such dramatic growth. Even RDRAM in which Samsung is the largest producer is shipping well to China," said Jon Kang, senior vice president of Samsung Electronics Co. Ltd.'s memory division.

The U.S. International Trade Office in Beijing estimates that China's chip sales this year will reach $19 billion, a 25% increase over 2001. The USITO projects that the China IC market next year will grow another 24%, to $23.6 billion, and climb 25% in 2004, to $29.6 billion.

Many foreign makers of memory chips are adding facilities in China to tap into the surging market. Samsung, which has a chip assembly and testing operation in China, is reportedly planning an initiative to expand its presence. Micron, which opened a module-assembly joint venture last year in Xiamen, is preparing to open a sales office in Shanghai.

DDR-III is expected to feature short-loop through (SLT), the signaling technique debuting in some DDR-II devices to reduce noise at high frequencies. Micron demonstrated a DDR-II chip with SLT at its JEDEX exhibition booth.

SLT eliminates "stubs" that branch off to carry the signal from the memory bus to each module in the system. The multiple data lines are vulnerable to greater noise at the very high frequencies of new-generation memory chips, said Dong Yang Lee, Samsung senior product planning manager. SLT connects a series of controller drivers directly with each memory module to reduce noise and signal reflection, he said.

The technique is aimed at servers to allow the addition of eight DIMMs per channel, or four times more than with the basic DDR-II configuration.

JEDEC sources at the conference said that SLT is similar to the technique used in Rambus Inc.'s RDRAM, a bitter competitor of DDR. They said that SLT is based on designs that go back to 1970 and aren't included in Rambus' patents.

JEDEC is also drafting an addendum to the DDR-II standard that would cover 2Gbit chips expected to come to market in 2005, sources said. The DDR-II spec also has been amended to double the number of memory banks to eight for chips of 1Gbit and above.

The increased number of banks reduces latency and boosts memory chip efficiency, according to the standards body.

All DDR-II memory modules will use new BGA packaging because of its smaller form factor, said David Chan, Infineon's applications marketing manager and chairman of the JEDEC DDR-II unbuffered DIMM working group.