MemoryLogix is not developing a full-fledged microprocessor, but rather a hybrid intellectual-property (IP) core that combines a 586-based central processing unit, MMX multimedia instructions, L1 cache, and a RISC-based "multi-fetch, scalar-execute pipeline" architecture.

The initial IP core, dubbed the MLX-1, will be a 400-MHz, 0.13-micron device that will compete in the embedded processor space against ARM Holdings, Mips Technologies, and others, said S. Peter Song, president of the Mountain View, Calif.-based startup.

The MLX-1 is geared to replace ARM's family of chips for cellular phones and other products, Song declared. "We are targeting system-on-a-chip applications," he said. "Think of our product as the ARM11, with an x86-based instruction set," he said, referring ARM's new ARM11 RISC-based processor line.

The startup is currently developing the MLX-1, with plans to ship the IP core product in late-2003, he said in an interview at the Microprocessor Forum.

Analysts, however, believe there could be some limitations--if not legal issues--with the MLX-1. Given the MLX-1 deploys a RISC-based pipeline architecture, Song acknowledged that there could be some x86-based compatibility issues with the company's IP core.

"We haven't discussed the compatibility issues yet," he told SBN. And during a presentation at the Microprocessor Forum, he said the company has build its IP core from the ground up--without obtaining an x86- or MMX-based license from Intel Corp.

The disclosure prompted fears of possible legal troubles with Intel. "Regarding MMX, we do have a work around," he claimed, without elaborating.

In any event, MemoryLogix hopes to bring a new and fresh approach to the embedded chip market. Formed about two years, the low-profile company was originally known as Elan Research, but it recently changed its corporate name to MemoryLogix.

The startup has received some venture capital financing, although it is currently looking for fresh funds, said Song, who held various management positions at Advanced Micro Devices, IBM, and other companies.

From its inception, MemoryLogix has been looking to solve a major problem: how to drive the venerable x86-based processor architecture into the tiny, low-power embedded space.

"The ARM10 RISC chip from ARM Holdings runs at 400-MHz, which is about half the speed of the x86-based architecture," Song said during a presentation at the Microprocessor Forum. "The problem is that the x86 architecture is ten times larger than the ARM10 in terms of die size," he said.

The ARM10 is 4.6-mm square in terms of die size, he said. The goal of MemoryLogix is to develop an x86-based IP core that is only two times the size of the ARM10. "We believe that an x86-based core can be made as small as the ARM10," Song said.

On the IP core, MemoryLogix hopes to cram a 586-based CPU, MMX, and a RISC-based "multi-fetch scalar-execute pipeline architecture." The multi-fetch pipeline is a "three-cycle bubble for handling branch instructions," he said.

The multi-fetch holds five 8-byte blocks, which pre-fetches up to three blocks from a sequential path. The IP core also consists of L1 cache, built around a "N-way set-associative" and a three-cycle access.