Cadence, which described the status of its "X Initiative" effort here at the Fabless Semiconductor Association expo, said the two test chip projects based on 130-nanometer design rules are well under way and that the prototypes should be finished by the first half of 2003. Cadence hopes to describe its work at a technical conference next year, said Aurangzeb Khan, general manager of Cadence's Design Foundry division.

The ARM device is a 200,000-gate chip based on the company's ninth generation processor (ARM9) core running at 225-MHz. Kahn said Cadence has already proved it can reduce the wiring by 20 percent and the via count by 14 percent. The company is also planning to take a second pass at the design to further reduce wiring by 25 percent and the number of vias by 20 percent compared to conventional "Manhattan" architectures which use orthogonal wiring schemes.

At the same time, Khan said it is working on an undisclosed IC project from STMicroelectronics to reduce wiring by 24 percent and the number of vias by 34 percent That should shrink the overall size of the 88,000 gate test chip by 20 percent compared to conventional wiring techniques, Khan said.

ARM and ST join Toshiba and subsidiary ArTile, which described a prototype processor earlier this year that uses diagonal interconnect, as possible early adopters of the so-called "X Architecture," which Cadence inhereted after its recent purchase of Simplex Solutions.

Cadence is also working with other chip companies on similar projects, though Khan declined to name them. Two possibilities include Matsushita and Sanyo, which are members of the "X Initiative" consortium.

So far, the projects with ARM, ST and others still in their early stages and there are no concrete plans to manufacture and sell chips based on the unusual wiring scheme. "At this point I would call it an R&D effort," Khan said. "Our goal is to demonstrate the benefits of this approach."

While Cadence and its X Initiative partners are drawing interest from some major chip manufacturers and developers, it still has its doubters. Altera Corp., for one, remains unconvinced that it would deliver benefits promised in its FPGAs, which are heavy users of on-chip interconnect. Diagonal routing, for example, could Altera's use of redundant wiring as a way to improve yield, something that DRAM manufacturers also employ, said Jordan Plofsky, senior vice president of Altera.

"(Diagonal interconnect) has been talked about for 20 years," Plofsky said. "Practically speaking I don't think we've run out of steam in Manhattan routing."

Khan admitted that diagonal interconnect should be attractive for fully-synthesized ASIC or customer-owned tooling (COT) designs but not necessarily for full custom or structured-custom designs. "Where X architecture shines is in designs using automated place and route," he said. "That's where the sweet spot of the market is. What consumes most silicon real state are the areas with automated place and route."

Cadence will eventually try to fold X architecture into a hierarchical design methodology that it is developing for 90 nanometer design rules. It has also started work on test chip vehicles using diagonal interconnect for that technology node, Khan said.

Other companies were on hand to make the case for the X architecture. Michael Sanie, director of marketing and business development at Numerical Technologies, described how his company was able to make diagonal interconnects work with optical proximity correction techniques, which is often employed to resolve chip features that are smaller than the minimum wavelength of the lithography tool. With diagonal interconnect, the end points of metal lines must appear more jagged than they normally would because they have to connect in eight directions rather than just four. This requires the use of more polygons at the end of a wire representation, but the run time of the tools "are within normal range," Sanie said.

KLA-Tencor, meanwhile, said it has 0.25- and 0.13-micron plates with diagonal interconnect TeraStar reticle inspection tool and that time it took prepare the data "were within expectations." Unlike earlier tests 18 months ago, no false defects were detected at the "elbows" of 0.25-micron features and overall defects were low. Few defects were found on the 0.13-micron plate, though the octoganal structures did cause some "nuisance defects," said Chris Aquino, applications manager at KLA-Tencor.