By changing the way the HBT is built, power consumption can be reduced by a factor of four, and peak frequency performance improved by 60%, compared with the existing process, the company said.

Details of the re-organized transistor were presented at the IEEE's Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) this week.

"Our full suite of passives along with RF/analog MOS and optimized silicon germanium carbon are designed to enable new products while allowing current reduction in existing products," said Vida Ilderem, director of RF/IF silicon technologies for Motorola, in a statement.

Motorola's process integrates an HBT with CMOS analog and digital functions on a single chip. Because the latest development was made on existing technology platforms, designers can use existing models, libraries and standard cell designs for the 0.18-micron and 0.35-micron BiCMOS processes.

Cutoff frequencies have been improved from 50-GHz to 80-GHz in 0.35-micron BiCMOS and to 120-GHz in 0.18-micron BiCMOS with a reduction in minimum noise figure from 0.9-dB to 0.3-dB. This performance was realized through both vertical and lateral scaling of the transistors, Motorola said.

"These are key metrics for the wireless mobile market. They are intended to enable our existing and future customers to offer leadership products to the cellular, wireless LAN and GPS markets with unprecedented levels of integration," Behrooz Abdi, vice president and general manager of Motorola's radio products division.

Motorola has introduced several products using its first-generation 0.35 micron SiGe:C process including the RF portion of its i.250 GSM/GPRS Innovative Convergence(TM) wireless platform. The 0.18-micron process was qualified in the first quarter of 2002, with products planned for early 2003.