SAN JOSE, Calif. -- Xilinx Inc. has added two FPGAs to the top end of its Spartan family of devices; the C2S400E with 400,000 system gates and 410 I/O pins and the XC2S600E with 600,000 system gates and 514 I/O pins. And in 2003, the company is planning to deliver a fifth generation of the Spartan family reaching towards higher gate densities and pin-counts.
Xilinx FPGA coverage is divided into two families; Spartan at the less complex, lower cost end of the spectrum and Virtex-II, with the option of diffused hard cores, such as PowerPC processors, at the more complex and more costly end of the spectrum.
The new Spartan devices provide customers with higher gate counts, and greater I/O to address a larger range of consumer applications historically served by Virtex-II devices, and third parties' gate arrays and ASICs.
"Based upon market research, we know that devices with up to 304 pins serve approximately 41% of the total ASIC market. The Spartan-IIE extension products, with I/O counts up to 514 I/Os, extend the available market served by Xilinx to 65% of total ASIC shipments," said Clay Johnson, vice president and general manager of the general products division at Xilinx, in a statement.
The new Spartan-IIE family members, XC2S400E (400,000 system gates and 410 I/Os) and XC2S600E (600,000 system gates and 514 I/Os), devices will be available in volume production in January 2003, priced at $27 and $45 per device respectively in 250,000 unit quantities, Xilinx said.
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