SAN JOSE -- Cadence Design Systems Inc. and PDF Solutions Inc. here today (March 13) announced plans to co-develop a line of yield-analysis software tools for making analog and mixed-signal chips.
The software tools will be designed to improve the performances and yields of chips from both fabless chip makers and integrated device manufacturers (IDMs), according to the companies.
Cadence and PDF Solutions have teamed up to provide a software solution based on Cadence's analog-oriented EDA tools and PDF's Circuit Surfer products. Circuit Surfer is a statistical circuit design exploration environment for maximizing the yields and performance of chips.
The tool helps chip designers estimate how manufacturing process variations, including transistor mismatch, will impact circuit performances. The incorporation of realistic worst-case modeling and RSM-based statistical design validation helps designers avoid over and under design of analog ICs with minimal overhead.
"Cadence's strength in analog/mixed-signal design solutions combined with our strength in yield-ramping solutions will provide customers with a way to pre-qualify designs so they yield right from the start," said John Kibarian, president and CEO of San Jose-based PDF.
"With ever increasing design and process complexity, you cannot drop a design into manufacturing and expect to achieve timing, speed, and yield targets within market windows," he said. "An understanding of the interactions between design and process is essential to good yield. With this agreement, a broad spectrum of designers now have access to the technology to do this."
Circuit Surfer, which will be integrated into Cadence's analog design environment, will be available from Cadence in the second quarter of 2001.
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