SAN JOSE -- In a move to break embedded-processing bottlenecks and to clear at least one legal hurdle in a U.S. patent suit, Lexra Inc. today launched a new 32-bit RISC processor core that's optimized for 0.13-micron processes.

The San Jose-based company claims its new central processing unit contains several key architectural enhancements to greatly boost data transfer speeds over existing CPUs based on the 32-bit R4000 from MIPS Technologies Inc., while also easing the job of using the core in ASIC design methodologies.

Lexra said the 420-MHz LX4380 reduced-instruction set computing core will enable system-on-chip designers to incorporate up to 64-kilobytes of on-board cache memory--using standard SRAM intellectual property blocks--and speed up data transfers by more than five times over other 32-bit CPUs. Lexra president and CEO Charlie Cheng said the new core is "100 megahertz and 100 million instructions per second better" than any other 32-bit MIPS-based processor on the market.

The LX4380 core is targeted at fabless semiconductor companies pursuing SoC designs for consumer and communications networking applications, such as digital subscriber line (DSL) multi-protocol ICs, interactive digital TV, and multimedia systems. One major problem facing these fabless chip companies has been optimizing CPU performance for other IP blocks--such as SRAM and I/O functions along with their own intellectual property cores. Lexra said its new 32-bit RISC brings embedded CPU performance much closer to that of customized processors while still enabling designers to more easily use ASIC technologies.

When fabricated in 0.13-micron processes from silicon foundries, the 32-bit RISC core will fit into a die area of 0.76 mm² (without memory), and it can handle up to 32 Kbytes of both instruction and data cache, according to the company. Lexra said it expects to see the first LX4380-based customer chip designs to be shipped in the third quarter of 2001, and the new core will be generally available in the fourth quarter this year.

The new RISC core is compatible with MIPS Technologies' 32-bit CPU, but it applies a seven-stage pipeline (instead of five) to increase performance, and it partitions critical-path elements into smaller blocks of logic to simplify optimization of SoC designs using commercially available ASIC design tools, said Lexra officials. A third architectural innovation in the LX4380 core is a new capability, called "background move," which reduces the amount of time that CPUs spend waiting for data transfers to be completed, Lexra said.

The new 32-bit processor and support software also eliminate a disputed feature in Lexra's existing RISC cores--instructions for unaligned loads and stores that MIPS Technologies claims violates one of its patents. MIPS Technologies has been suing Lexra for patent violations in its CPUs (see Sept. 29, 1999, story).

The LX4380 core's Linux kernel can be recompiled without the disputed instructions, and it removes support for emulating the unaligned load and store functions, said Jonah McLeod, director of corporate marketing at Lexra.

"We have eliminated this aspect of the instruction set, and they can no longer claim the core is violating their patent," said McLeod, who added that Lexra still maintains that its existing technologies are not infringing upon MIPS intellectual property rights. Late last year, Lexra argued that MIPS Technologies' patent claims on the unaligned loads/stores functions were invalid (see Dec. 11 story).

A single-license fee for RTL is $568,000 for the first project with a chip royalty fee of $0.85 per IC in quantities of 100,000. Lexra said its core has demonstrated that it delivers 420 MHz under typical conditions, and 360 MHz under worst-case process, worst-case commercial conditions for 0.13-micron ASIC technologies from silicon foundry giants Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and United Microelectronics Corp. (UMC).

--J. Robert Lineback