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Tessera--with Intel--introduces 'folded' stacked-chip packages
Initial flash products using 3-D packaging technology are expected to be introduced in early 2002
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Silicon Strategies


SAN JOSE -- Tessera Inc. today announced a development effort with Intel Corp. to radically reshape stacked-chip packaging. The new concept places multiple devices on top of each other by mounting them on a common flexible substrate, which is then folded like a piece of paper to stack chips in the vertical dimension.

Tessera's new "folded" stacked chip-scale package is designed to overcome a number of limitations in existing stacked-chip formats, including the ability to make packages extremely thin, said John Riley, vice president of the company's Wireless Business Unit here.

The initial prototypes of Intel's multi-die chip-scale packages will accommodate three devices with a total height less than 1 mm, according to Tessera. In comparison, other stacked-chip packages, based on wire-bonded assembly technology, are about 1.4 mm in height with just two devices inside the package, according to Riley.

The folded stacked packaging technology is expected to dramatically increase the volume of three-dimensional packages. This year about 200 million flash/SRAM stacked-chip units will be shipped in 3-D packages, using existing wire-bonded technology, according to estimates from Dataquest Inc. A little less than 100 million stacked DRAM units are expected to be delivered this year as well, according to Dataquest in San Jose.

"I think these shipments are well under the potential market volumes because of the limits of today's technologies," Riley said.

Using existing technology

Tessera's new 3-D package applies the same patented technologies that are now being used in the company's microBGA chip-scale package. Other than the final folding step at the end of the assembly process, no special materials, tools or processes are needed to produce the new folded chip-scale package, Riley said.

"We simply take multiple chips and mount them on a flexible substrate or printed circuit board. The substrate is folded into a footprint that is less than a single TSOP thin small outline package," Riley said. "The folded stacked-chip package is below the height of a TSOP, which is typically 1.2 mm," he added.

The mounting-and-folding concept to stacking chips in a single package is also simpler than wire-bonded assemblies, according to Riley. To wire-bond multiple chips inside a stacked package, companies must pass products through wire bonding tools multiple times, he said. An additional step is also needed to place a pad between chips to separate the dice, and extra clearance is needed for the wires than are bonded to the pads on the die, said the Tessera manager.

"It is a multi-step manufacturing process, resulting in higher costs and taller packages that cannot be shrunk while keeping stress inside the package at a minimum to meet the system requirements for shock and vibration," Riley stated.

The folded stacked package "can accommodate those stress requirements between different components inside the package because of the 'compliant' layer between each die is flexible," he added.

In addition to Intel, Tessera is working with other integrated device manufacturers and contract assembly houses to introduce the folded chip-scale package into production by the first or second quarter of 2002. Tessera will not identify the other companies.

In the future, folded stacked packaging technologies will be applied to a range of products, from cellular phones, to MP3 music players and other portable systems, predicted Tessera. The company believes four 128-megabit flash memories will be stacked inside the folded package with a height of just 1.2 mm--the same size as a single-chip TSOP. "This would give an MP3 player two houses of music in a single package that contains 64 megabytes of memory," Riley said.

'Cell phone-in-package'

Tessera also sees a range of ICs being packed inside the folded chip-scale package. For example, it is possible to fold together a baseband IC for cellular phones with two flash memories and two SRAMs in a package that is only 1.2 mm thick, according to Riley. "Our vision is for this technology to leverage silicon integration and packaging integration to make possible an entire cellular phone in a single stacked chip package, which would be necessary for something like a wristwatch phone or other wireless applications," he said.

Just as important as potentially shrinking the size of systems is giving equipment makers the ability to combine more features inside their products, Riley said. "Cell phone companies are a not so much focused today on miniaturization as they used to be when phones were larger," he noted. "People today are even complaining that cell phones are too small and getting lost! But the phone maker are now looking at combining more features in handsets, such as MP3 players and other applications."

Tessera is charging both an initial licensing fee and unit royalties for the folded chip-scale package. No extra licensing fees are paid by companies using Tessera's microBGA package since all the technologies are the same in the folded package, Riley said.

Initially the folded package will be slightly more expensive than wire-bonded stacked chip package, Riley said, but with increased volumes Tessera expects the costs to be driven below existing technologies.






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