TOKYO--Hitachi Ltd. here today announced development of a new embedded circuit technology that will reduce the operating power of synchronous DRAMs by 40% while improving data access times by 49%.

The technology--called "SDRAM Mode Control Scheme"--essentially enables SDRAM sense amplifiers to work like cache memory, making data available to central processing units without having to clock through the entire access cycle, according to Hitachi. The company said it believes this type of circuit could be embedded in CPU chips and other microprocessors to improve performance and cut power consumption.

The technology uses a circuit block taking up 0.28 square millimeters, said Hitachi, which is presenting a technical paper on the development at the Low Power Electronics and Design (ISLPED) 2001 conference in Huntington, Calif.

In conventional SDRAMs, memory is access in three steps. First, data is transferred from a cell to sense amplifier. The data is then made available on the output of the sense amplifiers. And then finally, the data is cleared in the sense amplifier. Hitachi concluded that if the data is not cleared but maintained in the sense amplifier, the circuit could operate as a cache memory, making data available to the CPU without working through the entire access cycle. This reduces power and speed availability of the data to the CPU, said the Japanese chip maker.

Hitachi said it has used several benchmark programs to evaluate the performance improvements of scheme. Those tests have shown a reduction of power consumption by 40% and speed improvement of 49%. Hitachi did not release information about when the circuit might be used in products.