The new business--called Intel Microelectronics Services--is a new and radical turnkey service that will help IC makers and OEMs bring their application specific integrated circuits (ASICs), application specific standard parts (ASSPs), or system-on-a-chip designs to the market more rapidly.

To help propel its new fabless ASIC business, Intel has forged an impressive list of alliances with EDA software, intellectual-property (IP), silicon foundry, IC-packaging and test providers. Among Intel's partners in its ASIC service include Synopsys, Chartered, TSMC, UMC, Amkor, ASE, and ChipPAC.

Surprisingly, the Santa Clara-based chip giant claims that it will not use its own wafer fabs in this new ASIC service. Instead, Intel will utilize three major foundries: Singapore's Chartered Manufacturing Pte. Ltd., Taiwan Semiconductor Manufacturing Co. Ltd., and Taiwan's United Microelectronics Corp.

Intel's service--which is mainly targeted for the communications-oriented chip market--also calls for Intel to provide CMOS-based 0.25- to 0.13-micron ASIC/ASSP designs. In addition, the company will manage every aspect of the IC design and production cycle, as well as the distribution services, for customers, said Craig Peterson, co-general manager of Intel Microelectronics Services, based in Hillsboro, Ore.

In other words, it will offer a "one-stop shop" of services-such as IC design, production, chip-packaging, and test--at a cost that is equal or better than the traditional ASIC houses, such as IBM Microelectronics, LSI Logic, and others, Peterson said.

"This is a recognition of the outsourcing model in the industry," he declared, referring to the trend among chip makers to embrace silicon foundries and chip-packaging subcontractors.

"The ASIC houses are only interested in filling up their factories," he said. "What we're trying to do is make it easier for ASIC customers," he said in an interview with SBN at Intel's headquarters in Santa Clara.

For example, instead of dealing with several complex contracts with EDA, foundry, IC-packaging, and related vendors, customers can simplify the entire design cycle process by interfacing with only one company--Intel, said Naveed Sherwani, who is the other co-general manager of Intel Microelectronics Services. "With this service, you only have to deal with one contract within Intel," Sherwani said in an interview with SBN.

With its new service, however, Intel will not go after the PC-oriented IC markets, he said. Instead, the company will limit its new fabless ASIC service to several communications-oriented markets, including broadband, local-area networking, wide-area networking, and wireless, he added.

In total, the communications-oriented ASIC/ASSP market is projected to hit $18.75 billion in 2001, according to Dataquest Inc. of San Jose.

The new service propels Intel into the ASIC business--albeit the new and emerging fabless portion of the market. The fabless ASIC business is still in its infancy, but it has some advantages over the traditional ASIC model, according to Dataquest.

"The key advantage of the fabless ASIC company business model is that it transfers a number of the fixed costs that are associated with a traditional ASIC company to third parties," according to a report from Dataquest. "The approach avoids the capital burden of owning costly fabs and packaging plants, developing process technology, creating intellectual property and tools," the report said.

Until now, the fabless ASIC business has been dominated by smaller companies, such as Dialog Semiconductor, eSilicon, and others, according to Dataquest.

Intel will also compete against others as well. "LSI Logic is mostly threatened by Intel's fabless ASIC service," said analyst Martin Reynolds of Dataquest, referring to LSI Logic Corp., the Milpitas, Calif.-based ASIC pioneer. "LSI Logic is moving towards a fabless ASIC model as well," Reynolds said.

Intel stands a good chance to succeed in this arena. "Intel's fabless ASIC model seems like a good idea," the Dataquest analyst said. "You can get Intel to help develop your ASIC and they manage the entire project," he said.

In fact, its ASIC service could grow from "tens of millions of dollars in sales" for the company in the first year alone, to perhaps "$100 million in revenues in the next couple of years," he added.

But still, Intel's ASIC service is unproven. It could also face an uphill battle in "gaining the confidence with potential customers," the Dataquest analyst said.

Meanwhile, Intel's service has some similarities and differences with the traditional, vertically-integrated ASIC model--which is also endorsed by IBM Microelectronics, Fujitsu, NEC, Toshiba, and others, according to analysts.

Like the traditional ASIC model, Intel's new service has a collection of internal IC design centers, which are located in four sites: Hillsboro, Santa Clara, Calif., Dupont, Wash, and Bangalore, India.

But Intel's service is fabless--which is somewhat shocking, given its plethora of cutting-edge fabs. And, the company will draw upon an impressive list of third-party providers.

On the EDA software side, for example, the company has formed an alliance with Synopsys Inc. Under the terms, Synopsys will provide potential customers with its Synopsys Professional Services. These services support the front-end of the chip design process, such as register transfer level (RTL), place and route, physical synthesis, and related functions.

Customers have the option to hand off their chip designs or concepts to Synopsys or Intel. "We are looking for designs with 100,000-to-200,000 gates," said Intel's Peterson. "We think that's the sweet spot in the market."

But that's not all. Intel, along with Synopsys, are also forcing alliances with "leading" third-party IP vendors, enabling customers to develop system-on-a-chip or related products.

"It could take two or three months to develop a relationship with an IP company," Peterson said. "We can make it easier by managing the relationships with IP vendors."

Once the design or "netlist" is completed by Synopsys, the Mountain View, Calif.-based EDA giant will turn the work over to Intel.

Intel, in turn, will provide the so-called back-end software design services. "We do the tape-out," said Peterson. "Then, we take the design to leading foundries. Then, we take it to the various packaging and test houses," he said.

Customers have the option to use three major foundries in Intel's new service, including Chartered, TSMC, and UMC. The program also enables customers to choose among three IC-packaging and test houses--U.S.-based Amkor Technology Inc. and ChipPAC Inc. and Taiwan's Advanced Semiconductor Engineering Inc.

If that is not enough, Intel will provide even more services. "We can even ship the finished product to your customer's location," he added.

Intel also will provide its customers with a real-time, online tracking service that will track their chip products from design-to-test, according to Sherwani.

Intel's online tracking service will gather the data from the various third-party foundries, he said. The data, in turn, will be available on Intel's own Web site, he added.