On the 64-bit side, AMD will unveil Hammer, a processor based on 0.13-micron and silicon-on-insulator (SOI) technologies. According to AMD's own roadmap, the company will officially ship three versions of Hammer in the second half of 2002.

The first version of Hammer appears to be a desktop processor, while the other two devices are geared for high-end workstations and servers. And in the distant future, Hammer could even migrate to the mobile space, according to AMD.

The higher-end Hammer device is code-named SledgeHammer, which is geared for four- and eight-way multiprocessing systems. Meanwhile, the code-named ClawHammer is geared for one- or two-way systems.

Analysts believe that AMD's Hammer is a showstopper. "Hammer is the highlight of the Microprocessor Forum," declared Nathan Brookwood, an analyst at Insight64 of Saratoga, Calif. "It leapfrogs everything in the market by a factor of two in terms of performance, including IBM's Power4," Brookwood said.

Brookwood was referring to IBM Microelectronics' high-end Power4 RISC processor line, which is geared for high-end servers. If or when AMD ships the Hammer in the market, the processor could also leapfrog Intel Corp.'s Itanium family of 64-bit processors and Sun Microsystems Inc.'s Sparc devices, according to analysts.

AMD did not provide the exact clock speeds of Hammer, but the company noted that the processor has an overall bandwidth performance of 8-gigabytes-per-second--or roughly four times faster than competitive devices. "The Hammer combines the advantage of CISC and RISC," said Fred Weber, chief technology of AMD, in a presentation at the Microprocessor Forum.

According to a presentation from AMD at the Microprocessor Forum, Hammer supports both 32- and 64-bit instructions. The processor itself consists of several blocks: a 32/64-bit MPU core, integrated double-data-rate (DDR) SDRAM memory controller, Level 1 instruction cache, Level 1 data cache, Level 2 cache, and HyperTransport I/O.

"It is designed to handle workloads very well," Weber said. "The basic pipeline is 12 stages long," he said.

The DDR SDRAM memory controller consists of 8- or 16-byte interfaces and supports the PC1600, PC2100 and PC2700 standards. The Level 1 data and instruction caches support 64-kbytes of memory, while the Level 2 cache handles 1-MB of memory.

Another key to Hammer is the company's HyperTransport technology, a high-speed, chip-to-chip I/O architecture. HyperTransport enables two- to eight-way multiprocessor systems, according to AMD.

The Hammer is a "very-wide super-scalar processor," according to a Web site called Chip-Architect.com. The 64-bit processor from AMD also "contains a double core. Both cores are loaded with functional units to execute the instructions," according to the Web site.

The processor has other key features as well. "The pipeline supports not less then six instructions in parallel, twice as much as the current Athlon," according to the Web site. "Most innovations in the Hammer are intended to make it the X86 processor with the highest Instruction Level Parallelism yet and should make it a very powerful single thread processor," the Web site said.

"Innovative new units like the 'ESP Look Ahead unit' and the 'Forward Collapse unit' should help to extract an unprecedented level of instruction level parallelism from the good old X86 instruction architecture to feed all the hungry functional units," according to Chip-Architect.com.

Meanwhile, Sunnyvale-based AMD has rolled out its latest Athlon MP line of microprocessors for servers and workstations. Dubbed the Athlon MP 1800+, 1600+ and 1500+, the new processors feature the company's so-called QuantiSpeed architecture and Smart MP technology.

The new Athlon MP processors are designed for one- and two-way servers and workstations, said Ed Ellett, AMD's vice president of AMD's Computation Products Group.

The model numbers are strategically aligned with AMD's recently announced True Performance Initiative, which seeks to assist customers in understanding the benefits of processor performance. TPI also will help define a new, more accurate measure of processor performance for standard applications (see Oct. 9 story ).

AMD claims the devices have distinct performance advantages over competitive chips. For example, a workstation based on a dual 1.53-GHz AMD Athlon MP processor 1800+ outperforms a similarly-configured workstation based on a dual 1.7-GHz Intel Xeon processor by up to 23%, according to AMD.

The AMD Athlon MP processors 1800+, 1600+ and 1500+ are priced at $302, $210 and $180, respectively, in 1,000-unit quantities.