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Gate shrinks in MPUs could hit 'wall' in six years, says 2001 industry roadmap
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Silicon Strategies


SAN JOSE -- The acceleration of transistor-gate shrinks in microprocessors has put the chip industry on a path to hit some fundamental limits in process technology in just six years, according to a new international technology roadmap released today by the Semiconductor Industry Association here.

The recently completed 2001 International Technology Roadmap for Semiconductors (ITRS) shows transistor-gate lengths in microprocessors shrinking to just 25 nanometers (0.025 micron) by 2007, which is six years earlier than projections in the 1999 version of the roadmap.

The rapid shrink of gate lengths is partly a result of processor manufacturers using post-lithographic process techniques to selectively reduce those feature sizes beyond the minimum printed geometries in photoresist. Smaller gate lengths increase the speed of microprocessors, which increases the average selling prices of those ICs.

However, transistor-gate lengths in microprocessors could quickly exhaust known technology options for additional shrinks beyond 2007, suggested experts, who drafted the 2001 technology roadmap. The new ITRS document now distinguishes "physical" gate lengths from gate lengths "printed in photoresist" as a result of the selective gate shrinks in MPUs.

The new roadmap sets industry technology targets and milestones for the next 15 years, updating the last official ITRS issued in 1999. Overall, the 2001 ITRS document accelerates the scaling--or shrinking--of feature sizes in processors, memories, and ASICs, compared to the 1999 roadmap.

At the end of the 2001 ITRS document--which is set at 2016--the minimum physical gate length of transistors is now projected to be just 9 nm (0.009 micron). Roadmap officials said this is essentially equivalent to the most optimistic current projections on the extendibility of MOS transistors as well as the smallest experimental MOSFETS ever built.

Currently, leading-edge IC products are in the 0.18-micron (180-nm) technology node, with 0.13-micron (130-nm) devices now beginning to reach the marketplace, said the SIA. The new technology roadmap moves up most of the DRAM technology nodes for critical dimensions by about one year, compared to the 1999 ITRS document.

For example, the 100-nm (0.10-micron) generation in DRAMs was set expected to move into production in 2005, based on the 1999 roadmap, but now industry experts predict that DRAMs will reach 90-nm half-pitch feature sizes in 2004. The 1999 roadmap showed the 70-nm node moving into production in 2008, but now the new roadmap has 65-nm DRAMs in wafer fabs during 2007.

The 1999 roadmap set the 50-nm node in 2011 but now 45-nm technology is expected to be used by DRAM makers in 2010. The new roadmap also shows DRAMs at the 32-nm node in 2013 vs. 35-nm in 2014. The newly identified 22-nm technology node is expected to be used in 2016, according to the 2001 ITRS roadmap.

"Lithography half-pitch and transistor-gate length scaling trends continue to accelerate," noted Paolo Gargini, chairman of the International Roadmap Committee and a fellow at Intel Corp.

He said the prospects of 9-nm "physical" gate lengths in microprocessors by 2016 is causing the industry to "consider technologies beyond planar or even post-CMOS devices."






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