As reported, Intel Corp. today announced a new transistor structure that marks the company's initial use of high-k dielectrics, epitaxial wafers, and a real surprise--SOI. The new TeraHertz transistor structure from Intel will become the company's key building block for future, low-power microprocessors (see today's story ).

Until now, meanwhile, Intel has dismissed the need for SOI, claiming it does not require the technology for processor designs, especially its current Pentium 4 chips. But others, notably IBM Microelectronics, have been using traditional SOI technologies for processor designs since the late-1990s. And another rival, Advanced Micro Devices Inc., plans to use similar SOI technology for its next-generation processors as well (see July 13 story ).

AMD also plans to use SOI for its next-generation, 64-bit processor, code-named Hammer. Earlier this month, Silicon-On-Insulator Technologies (Soitec) of France announced a multi-million dollar order for 200-mm SOI wafers from AMD, which plans to use the substrates to produce its recently announced"Hammer" series of 64-bit microprocessors (see Nov. 12 story ).

Officials from Intel denied that it's behind AMD, IBM and others in this space, claiming that it will skip traditional SOI wafers and move to a next-generation technology called "thin SOI" or fully-depleted SOI.

Ironically, Intel could turn to Soitec for its "thin" SOI wafers in the future, but the company declined to comment on its suppliers. "We are working with several SOI suppliers," said Rob Willoner, technology analyst at Intel of Santa Clara. "Soitec is the biggest player in the market," Willoner said.

At present, however, Intel does not use SOI wafers for its current processor designs. "We have always said that SOI was not useful for our current 0.13-micron generation chips," he explained.

"We believe that traditional SOI wafers cost many times more than bulk silicon--sometimes five to six times the cost," he said. "We've also had low-junction capacitance in our processors. So, SOI would not help us out very much."

But Intel claims it never ruled out using SOI wafers despite dismissing the technology in numerous interviews with company officials. "Intel has looked at SOI for many years," he said. "We've been opened-minded about SOI."

Officials from Intel claimed that "thin SOI" or fully-depleted SOI has several advantages over competitive technologies. The "thin" SOI wafers prevent leakages through the chip substrate, lower junction capacitance, and reduce overall voltages in chips, the company claims.

Cost is another issue. With "thin" SOI wafers, Intel may be able to lower the cost of this technology for mainstream chip applications, according to the company.

But one SOI vendor claims the technology is already in the mainstream. Bernin-based Soitec claims it uses both ion implantation and wafer bonding technologies to develop low-cost SOI wafers. "SOI is a sandwich-like substrate in which the silicon surface is electrically isolated from the substrate by an insulator," according to Soitec.

Several chip makers have moved into production using Soitec's SOI material, based on partially depleted device technology. But as IC feature sizes continue to shrink down to 0.10-micron and below, "device technology is moving from partially depleted to fully depleted silicon layers," according to Soitec.

"This translates into SOI having a decreasing silicon layer thickness, requiring new solutions that address the uniformity requirements associated with chip manufacturers' thin-film needs," they added.