Meanwhile, Intel's new transistor--called the TeraHertz transistor--is expected to become the company's key building block for the development of 10-to-20-GHz processors by the second half of this decade. But the company also dropped hints that it could use pieces of its TeraHertz technology in its next-generation, 0.09-micron (90-nm) chips, which are due out in 2003--or sooner.

At the International Electron Devices Meeting (IEDM) in Washington D.C. from Dec. 2-5, Intel is expected to present a paper about this technology for 50-nanometer transistors at the 90-nm node.

Beyond overall chip performance, the new transistor architecture will address another critical issue: If processors continue to use conventional transistors, then future devices could one day dissipate as much power as a nuclear plant--or even the sun's surface, according to the Santa Clara-based company.

"Power dissipation is getting out of hand," warned Rob Willoner, technology analyst for the Technology and Manufacturing Group at Intel. "The power issue is the number one challenge for processor design in this decade," Willoner said in an interview with SBN.

Intel claims the TeraHertz transistor will keep the power dissipation levels somewhat constant in future processor designs. "We want our future processors to be at least in the 100-Watt range," Willoner said, noting that Intel's current Pentium 4 processors run at 45 Watts. "We also plan to reduce the voltage in our devices by 15% with each new process generation," he said. "This represents a 30-to-35% reduction in power," he added.

According to Intel, the three key enablers to this new transistor structure--high-k dielectrics, epi, and SOI--are process-independent steps that will appear in the company's chip designs over time. "We are beyond the lab stage," Willoner said. "We expect to fully deploy the TeraHertz transistor by the second half of this decade. But we could see some of the pieces before that."

New bag of tricks

But to address the power issues, Intel believes it must re-invent the wheel in semiconductor technology--the transistor, which was discovered by William Shockley and other scientists at Bell Telephone Laboratories back in 1947.

In simple terms, Intel's TeraHertz transistor appears to be a souped-up conventional transistor with three new elements: chip-scaling technologies, high-k dielectrics, and a so-called "depleted substrate transistor."

The "depleted substrate transistor" itself consists of two distinct parts: a "thin" SOI technology and a "raised source-and-drain" structure.

To develop this transistor in the fab, Intel will also resort to a whole new bag of chip-manufacturing tricks. For example, in the "depleted substrate transistor" portion of this device, Intel will use SOI as an insulator and epitaxial wafers to "raise" or "thicken" the source and drain of the transistor.

The company will also replace the gate-based silicon dioxide layer of a transistor with high-k materials. High-k will make use of an emerging technology called atomic-layer deposition. And not to be outdone, the new transistor structure will make use of advanced lithography tools to scale the devices.

IC scaling and Moore's Law

The TeraHetz transistor appears to represent a revolutionary step for Intel's chip development efforts. At present, Intel's fastest 2-GHz Pentium 4 processor is a 42-million transistor device.

By 2007, the company hopes to develop processors with 1 billion transistors. It is also expected to develop a 10-GHz processor by 2005 and a 20-GHz chip by 2010 or so, according to analysts.

Going forward, Intel believes it will face few problems to boost the processor speeds with traditional bulk silicon, thanks in part to Moore's Law. Devised by Intel co-founder Gordon E. Moore, Moore's Law is a popular axiom that says the number of transistors in integrated circuits will double every 18 months due to device shrinks and other chip-processing technologies.

In the laboratory, Intel has already scaled transistors that could enable the development of high-speed chips in the future. This month, for example, Intel claims it developed the world's smallest transistor--a 15-nanometer device that will be used to make microprocessors and other chips by the end of this decade.

Intel's 15-nm transistor (gate-length) is a CMOS-based, 0.8-Volt device, said to handle switching speeds of 0.38-ps--or 2.63 trillion switches per second. Intel's 15-nm device is expected to become a key element in the development of 0.03-micron (30-nm) chips on 300-mm wafer substrates by 2009 or so (see Nov. 15 story ).

The company believes it can scale these tiny transistors by using various advanced lithography tools, including 157-nm scanners and extreme ultraviolet technology (EUV).

While Intel claims it can solve the scaling issues, the company faces another major hurdle in chip design: By using conventional transistors, the power consumptions of future devices could rise exponentially to some 100 Watts per square centimeters on the die--or roughly the equivalent of a nuclear power plant.

To solve these issues, Intel claims that it must re-engineer the transistor. The transistor is a simple device that consists of several parts: the gate, channel, source and drain. Below the gate of a transistor is a thin layer called the gate dielectric, which is made of a material called silicon dioxide.

Typically, the transistor functions as an electronic switch. When voltage is applied to the transistor, the gate serves as the on/off switch for electrons that move from the source to the drain via a channel.

But there are several problems associated with current transistors. Besides the apparent power issues, these devices are subject to excessive gate and transistor leakages, off-state leakages, soft-error rates, among other problems, according to Willoner.

Intel's TeraHertz transistor performs the same tasks as the conventional transistor, but the new structure is said to solve the inherent power dissipation and voltage problems in chips.

SOI and epi to the rescue

The TeraHertz transistor looks like a conventional transistor, but it also includes high-k dielectrics and the "depleted substrate transistor." The "depleted substrate transistor" itself is sub-divided into two parts: a "raised source-and-drain" structure and "thin SOI."

The SOI technique creates the transistors on a thin top silicon layer that is separated from the silicon substrate by a thin insulating layer of glass or silicon dioxide. This, in turn, increases transistor switching speed by reducing capacitance.

Until now, however, Intel has dismissed the need for SOI, claiming it does not require the technology for current processor designs. But others, notably IBM Microelectronics, have been using traditional SOI for processor designs since the late-1990s. And another rival, Advanced Micro Devices Inc., plans to use similar SOI technology for its next-generation processors as well (see July 13 story ).

Intel denied that it's behind its rivals, claiming that it will skip traditional SOI and move to a next-generation technology called "thin SOI" or fully-depleted SOI (see today's story ).

In another departure from its current designs, Intel will also resort to a new planarization technology. Typically, silicon transistors are made by using a flat planar process technology.

In the future, Intel plans to "raise" or "thicken" the source and drain on the conventional transistor, thereby reducing resistance by 30% and increasing the mobility of electrons in the device.

In doing so, Intel, for the first time, plans to use epitaxial wafers. Epi wafers makes use of a modified planar process that deposits an oriented layer of lightly doped silicon over the silicon substrate.

High-k moves into action

Another key to the new transistor structure is improvements in the gate dielectric. In chip designs, unwanted current flow is moving across the gate dielectric, based on a silicon dioxide material. "We have reached our limits in gate oxide," Willoner said.

In the TeraHertz transistor, Intel hopes to replace silicon dioxide with a new material with a "high k" value, reportedly In the 15-25 range. Current silicon dioxide has a value of 3.9 or so. The new high-k material also promises to lower gate leakage by 10,000 times over current silicon dioxide methods.

To enable high-k materials, Intel hopes to use a chip-manufacturing technology called atomic-layer deposition. Semiconductor-equipment vendors like Applied Materials, Genus, and others are developing atomic-layer deposition tools.

This process deposits films one atomic layer at a time--at a thickness of less than 100 angstroms, according to analysts. A variant of chemical vapor deposition, the technology uses a sequence of reactions to obtain a single-layer deposition that is self-limiting. Once the exposure achieves a complete single-layer reaction, no more deposition can occur until the process is repeated.

While Intel has the technologies in place to devise the TeraHertz transistor, the company still faces some major hurdles going forward. "We need several years before all of the bugs are worked out," Willoner added.