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Taiwan's ASE prepares 300-mm wafer-bumping line for volume production
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Silicon Strategies


KAOHSIUNG, Taiwan -- Advanced Semiconductor Engineering Inc. today announced it has completed development of 300-mm wafer bumping technology for flip-chip packaging.

A fully automated solder-bumping line for 300-mm (12-inch) wafers will be installed by ASE before the end of this year with customer qualification tests scheduled to begin in the first quarter of 2002. The contract chip-assembly and testing house said the 300-mm bumping line will be capable of handling 5,000 wafers per month.

"With an area 2.25 times larger than a 200-mm 8-inch wafer, 300-mm wafers can greatly lower production costs and boost capacity," said J.J. Lee, vice president of research and development at ASE.

Taiwan-based ASE said it has applied for over 30 patents related to its work in developing solder bumping processes for different sizes of silicon wafers, from 150-mm (6-inch) to the larger 300-mm diameter substrates. The company said its 200-mm wafer bumping technology has offered yield rates of 99.0% and is qualified by major independent device manufacturers (IDMs) from around the world.






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