SAN FRANCISCO -- At the International Solid State Circuits Conference here, five winning teams were awarded $20,000 each in the first phase of the Copper IC Design Challenge sponsored by Semiconductor Research Corp., the university-industry chip research consortium.
The second and final phase will culminate at Semicon West 2000 here in July, when first, second and third place winners will be honored.
A total of $1 million is at stake: $150,000 in cash prizes and $850,000 in technical services and design implementation support. Besides SRC, industry co-sponsors include Novellus Systems Inc., United Microelectronics Corp. and SpeedFam-IPEC Inc.
The top five Phase One winning proposals came from Carnegie Mellon University, led by professor Gary Fedder; Georgia Institute of Technology, led by professor James Meindl; North Carolina State University, led by professor Paul Franzon; University of Florida, led by professor Kenneth O; and University of Minnesota, led by professor Ramesh Harjani.
The submissions leveraged copper interconnects and have focused on five areas: interconnect architecture, digital implementation, mixed-signal implementation, technology/component and wireless/RF (radio frequency).
The contest's objective is to engage university faculty and students in creating original circuit designs that will help speed the adoption of new semiconductor copper technology. According to the contest sponsors, the advent of copper interconnects will lead to new design architectures that can singificantly improve the functionality and performance of ICs. The sponsors hope to tap into the creativity at leading engineering universities to speed the adoption of new approaches to chip design at the 0.18-micron node.
Fifteen teams have now been selected from the field of 43 teams representing 34 North American universities to participate in Phase Two.
"In this next round, all 15 participating university teams will have the opportunity to submit a winning IC design that uses the enhanced properties of copper interconnects to improve circuit performance and functionality," said Larry Sumney, the SRC's president and CEO, based in Research Triangle Park, N.C. "We hope that the design knowledge that we have gained with the implementation of this contest will prove valuable to the semiconductor industry as we move to copper as the new interconnect metal for sub-0.18-micron technologies."
Last July, 44 university teams submitted design proposals to compete in Phase One of the contest. The universities' paper designs were evaluated by a panel of judges made up of representatives from the SRC and the contest sponsors. Participants had access to UMC's 0.18-micron process copper libraries, provided free by Artisan Components Inc. in partnership with UMC..
Phase Two of the contest will be conducted during the spring 2000 semester. During this phase, the 15 participating teams will enter their layouts (in GDSII format) for actual silicon fabrication at UMC. The fabricated devices will then be returned to the contestants for test andevaluation. Contestants will then be expected to submit measured performance data and a discussion, comparing this data with simulation data, to the judges.
The final winners will be invited to present their designs at Techcon 2000 in Phoenix.
A $30,000 first-place award will be made to the winning team's university in the name of the team leader. A $20,000 second place award and a $10,000 third place award will also be granted. The cash prizes will support IC design education programs at the universities and allow a monetary reward for participating students on the winning teams.
The evaluation criteria for Phase Two will focus on creativity of design, impact of the design on future applications, design efficiency, test procedures, correlation of test results to the design performance predicted in Phase One and completeness of the materials submitted. All rights to
designs submitted remain with the university or universities from which they originate.
Phase One winners and their projects:
Carnegie Mellon University -- Micromachined Tunable On-chip High-Q Resonator
Georgia Institute of Technology -- High Performance Clock and Power Distribution Networks for Gigascale Integration Using Copper Interconnects
North Carolina State University -- A High-Speed & High-Capacity Single-Chip
Copper Crossbar
University of Florida -- A Wireless Clock Distribution System: Clock Receiver and Transmitter Circuits
University of Minnesota -- RF Front-End Design with Copper Passive Components
Phase Two finalists:
Illinois Institute of Technology -- ESD Protection Design Using Copper
Interconnects; More Robustness and Less Parasitics
Kansas State University -- Design of Integrated RF Bandpass Filters and Oscillators Using Copper Interconnects
Michigan State University -- Micro-learner: a Self Programming Engine
for Real-time Estimation, Prediction and Control
North Carolina State University -- Monolithic Copper Integrated Circuitry
Supporting Multi-layer MEMS
Ohio State University -- High Performance GHz RF CMOS IC's for Integrated Phase-Locked Loops
Rensselaer Polytechnic Institute -- Crosstalk Checker
University of California at San Diego -- Fast and Reconfigurable Image Compression System-on-Chip for Mobile Communication Using Copper Technology
University of Illinois at Champaign-Urbana -- The Design of New Current-Mode Sense
Amplifiers for High Speed DRAM with Copper Interconnects
University of Virginia -- Routing VIAs and Other Optimizations for Copper Interconnects
Yale University -- The UltraC2K: A Wire-Intensive Superscalar Processor
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