HSINCHU, Taiwan -- The race to offer advanced prototyping IC-processing services with multi-project wafers is heating up between the world's two largest silicon foundry companies here. United Microelectronics Corp. today announced an expansion of its multi-project wafer program to include the company's new 0.13-micron copper logic process technology as well as dedicated "Silicon Shuttle" wafers for advanced mixed-signal and radio-frequency CMOS devices.

UMC also said it intends to speed prototype shipments from multi-project wafers by reducing fabrication cycle times with a "hot-lot" schedule that puts substrates on a fast-track for completion in its fabs. Under the hot-lot schedule, each photolithography layer will be completed in about one day. Fabrication of multi-project wafers with six-layer metal and 0.18-micron feature sizes will be completely finished in UMC fabs in less than four weeks, according to the company.

UMC's expansion of its Silicon Shuttle program comes one month after rival Taiwan Semiconductor Manufacturing Co. Ltd. announced it was planning to increase its multi-project wafer shipments by 50% in the first half of 2001. TSMC is also extending its "CyberShuttle" multi-project wafer program to include its new 0.13-micron copper process technology (see Oct. 20 story).

Multi-project wafers have become increasingly important for the large foundries, which are now attempting to move customers to their most advanced technologies. Multi-project wafers enable foundry customers to cut costs by sharing photomask sets and processing steps because multiple IC designs are packed on a single silicon substrate. The cost of photomasks are rocketing with the price tag of some reticle sets being as high as a half million dollars.

The two foundry rivals--TSMC and UMC--both see multi-project wafers as being crucial enticements for customers to try their latest process technologies for new product designs that could eventually become high-volume runners. Multi-project wafers are also seen as a viable way to serve low-volume products, especially as foundries begin to increase their use of larger 300-mm wafers.

UMC's Silicon Shuttle program "opens the door" for companies wishing to benefit from the company's 0.13-micron copper and low-k logic platform, said Jim Kupec, senior vice president of worldwide marketing for the Taiwan foundry company. "The shuttle enables 0.13-micron product prototyping to be extremely affordable, making this advanced process more widely available to a broader range of new and existing customers," added Kupec, who is based in Sunnyvale, Calif.

Several 0.13-micron "WorldLogic Silicon Shuttle" wafers for logic and mixed mode technology are scheduled in 2001, said UMC. The 0.13-micron logic platform features copper interconnects with low-k insulator (k = 2.7). The transistor switching delays in the 0.13-micron technology is below 10 picoseconds, which UMC said will enable microprocessor clock frequencies in excess of 1 GHz.

Analog options are being offered on dedicated 0.13-micron mixed-signal wafers, which UMC said will enable system-on-chip functionality. These options include metal-insulator-metal (MIM) capacitors, low threshold voltage transistors, and copper inductors.

UMC's hot-lot schedule for multi-project wafers is a "first in the foundry industry," according to Peter Chang, chief executive officer of UMC. He said the fast-turn service will make leading-edge prototyping affordable.

Several of UMC's Silicon Shuttle options--low-Vt transistors, MIM capacitors, and inductors--are being aimed at prototyping services for Bluetooth devices. UMC said it has worked with Bluetooth system makers and intellectual property (IP) creators to develop new RF CMOS technologies as replacements for BiCMOS devices used in wireless connection systems.