The wafer stack was developed by Tachyon Semiconductor (Singapore) Pte. Ltd., the Singaporean subsidiary of Tezzaron, based in Naperville.

Each of the wafer stacks contains 3 or 4 eight-inch wafers. Before being bonded into a stack, each wafer was patterned with tiny connectors embedded vertically in the silicon. The connection process is based on the company's proprietary Super-Vias technology.

Cross-section micrographs reveal the wafer alignment is precise to within 1/3 micron, providing overlap for connectivity. The Super-Vias are 4 microns in diameter, embedded at densities as high as 14,000 per square millimeter.

Some of the Super-Vias were positioned to pierce only one wafer. Meanwhile, others were designed to interconnect with Super-Vias on other wafers. Wafer alignment during the bonding process allowed these Super-Vias to interconnect according to design, creating conductive paths that pierced two or more wafers.

In addition to providing electrical connectivity, Super-Vias address the worrisome issue of thermal buildup. Copper Super-Vias act as efficient radiators, dissipating heat that would otherwise be trapped between the silicon layers. The company minimizes thermal buildup by ultra-thinning each bonded wafer to a depth of only 13 microns.

Tachyon believes that future stacks can be built with smaller Super-Vias at higher densities.