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Intel, Samsung join IMEC's 300-mm, sub-45-nm project
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Silicon Strategies


LEUVEN, Belgium -- Intel Corp. and Samsung Electronics Co. Ltd. have joined Infineon, Philips Semiconductors and STMicroelectronics in a project based around the 300-mm diameter research wafer fab being constructed by IMEC, the independent research group, based here.

The five companies are core members of a collaborative research project that aims to develop key parts of future sub-45-nm manufacturing process technologies.

The research platform includes seven individual industrial affiliation projects that other companies are joining but core partners join all seven projects and get a say in influencing the development of the overall program, according to Luc Van den hove, vice president of silicon process and device technology at IMEC.

These are: advanced lithography, cleaning and contamination control, substrate modules, gate stack research, alternative CMOS devices, germanium-based CMOS devices, and advanced interconnect solutions.

Neither Van den hove, nor Gilbert Declerck, president and chief executive of IMEC, would discuss what the core partner companies are paying to for their position in the platform.

"The individual projects cost between 500,000 euro and two million euro (to join - about $600,000 to $2.4 million)," said Van den hove. The projects run for between three and five years. For another perspective Declerck said he expected the 300-mm wafer pilot line, due to open in May 2004, to cost about 160 million euro (about $200 million) to run each year and that IMEC is looking for 8 to 10 core partners maximum.

IMEC said that Texas Instruments Inc. was also a strong supporter of the CMOS research program, having signed up to a number of the individual projects.

"We are confident that more key players will join us and further extend our programs with worldwide competences," said Declerck in a statement.

Van den Hove said the consortium would work on a number of device and process module aspects of 45-nm and sub-45-nm process technology research. These would include FinFETs, fully-depleted silicon-on-insulator, strained silicon, high-k gate stacks. "It is not the goal of this program to produce a fully working 45-nm CMOS process. We do process module and device comparison work but the full optimization may be done elsewhere, such as at Crolles2," he said referring to the 300-mm research and pilot line facility shared by Philips, STMicroelectronics and Motorola Semiconductor Products Sector at Grenoble, France.

However, Motorola SPS, which is pursuing an "asset-light" approach to manufacturing and is the midst of a spin-off from its parent company, is notable by its absence from the IMEC project.

Van den hove, said efforts are being made to keep the 45- and sub-45-nm project complementary to research made by International Sematech.






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