Intel's 10-Gbit/s device will have the same basic architecture as its existing IXP1200, but with "significant enhancements" to accommodate the higher line speed, said Matthew Campbell, an engineer with the network processor division of Intel. Those enhancements, made to prevent memory access from slowing down the chip, should enable Intel to carry the IXP1200 foundation up to the OC-768 (40-Gbit/s) level, Intel officials told EE Times.

Intel fellow Matthew Adiletta will present some of the changes and demonstrate the part in simulation at the Intel Developer Forum here. Intel plans to discuss its network processor plans at IDF sessions on Thursday as well.

Adiletta will present a road map that shows the 10-Gbit/s device as the foundation for OC-48 (2.5-Gbit/s) and OC-3 (155-Mbit/s) NPUs, which will be stripped-down versions of the 10-Gbit/s part. This will allow Intel to maintain a common architecture across a wide range of speeds, but will also bring Intel to the OC-48 market late, as devices from Agere Systems Inc. and others are already shipping at that speed.

Intel's OC-192 (10-Gbit/s) device is due to tape out in early 2002, and Intel won't reveal details of the new architecture until October, but Adiletta is expected to explain some of the enhancements to the part.

Sticking points

Specifically, Intel is sticking to its store-and-forward architecture, in which all packets are stored in memory and examined by a set of programmable RISC-based processing engines. This arrangement has been eschewed by many NPU startups due to the number of memory transfers it can incur, but Intel contends it has massaged the IXP1200 architecture sufficiently for OC-192 processing.

Intel's goal was to allow a modified IXP1200 to handle OC-192 packet processing while using standard external memory. That approach contrasts with those of such startups as EZchip Technologies or Silicon Access Networks Ltd., which rely heavily on embedded memory for their OC-192 NPUs. Campbell wouldn't say what external memory architecture is being considered for Intel's OC-192 solution, but he did say it's an existing architecture.

To avoid bandwidth problems, Intel will allow the NPU's multiple RISC engines to operate as a functional pipeline or a contextual pipeline. In the former case, successive processing engines handle one piece of the processing, then pass a packet to the next engine. In contextual pipelining, an engine performs multiple functions on a particular packet, thereby trimming the number of memory accesses required.

Intel's 10-Gbit/s device will allow for an arbitrary mix of functional and contextual pipelining so that users can tailor the pipeline to meet the available amount of memory bandwidth, Campbell said. To help with configuration, Intel has developed a tool to measure available memory bandwidth for a particular configuration and will recommend configurations for common functions such as packet classification.

Intel also will add "ring buffers" between the microengines. These will be small segments of memory that allow packets to sit in a "holding pattern" in case the next microengine is busy, giving the pipeline a bit of flexibility in its timing. "The ring buffer performs this elasticity function so you don't have to have things perfectly synchronized," Campbell said.

Each microengine also has its own cache memory, so a packet can be held for successive microengine threads without being shuttled to and from external memory. "You lock it in until it's all processed, then you stream it to memory," Campbell said.

Engine changes

OC-192 processing also will require changes to the RISC microengines themselves, but on a small level. "I'd say it's akin to when we changed the microarchitecture of the Pentium III to Pentium 4," Campbell said.

Adiletta's Wednesday demonstration of the 10-Gbit/s part in simulation is critical because it's a step further than many other 10-Gbit/s NPUs have gotten, Campbell said. It's important to have simulation models ready at this stage to help OEMs prepare their code and applications while waiting for silicon to be available, he said.