The technology, dubbed P1265, represents Intel’s first process that is tailored for ultra-low power chip applications, such as cellular phones, PDAs and other products, said Mark Bohr, senior fellow and director of process architecture and integration at Intel (Santa Clara, Calif.).

Slated to ramp up in the 2007 time frame, the P1265 process has demonstrated the ability to reduce transistor leakage by roughly 1,000 times over its current 65-nm technology for high-performance processors, Bohr said. Intel said that it has also manufactured a 50-megabit SRAM test chip, based on the technology. The test chip is a 350-million transistor device with a cell size of 0.68-micron².

To enable P1265, Intel has modified its 65-nm process in three areas: the sub-threshold voltage, ultra-shallow junction and gate oxide.

But the technology does have some trade offs in performance. “Intel’s ultra-low power process is a significant part of Intel’s strategy to reduce platform power,” he said in an interview. “But the transistor performance is lower by a factor of two” compared to the company’s high-performance 65-nm process.

Still, power is the name of the game at Intel and other chip makers. For example, AMD, Intel and others have been scrambling to devise multi-core microprocessor designs in an effort to mitigate power consumption and leakage.

Texas Instruments Inc. claimed Monday (Sept. 19) it had solved the problem of excessive leakage current at the 65-nanometer manufacturing process node with the transfer of its SmartReflex power and performance management technologies from the 90-nm process node to the 65-nm node.

The SmartReflex technologies are a combination of adaptive devices, circuit design and software designed to solve power and performance management challenges at smaller process nodes, TI said. This is instead of or in addition to specifically attacking gate leakage current through the use of high-k gate insulator materials, a quest that has been pursued by the industry for many years (see Sept. 19 story).