EEdesign exclusive: EDA vendors set 2003 priorities

There's been a lot of effort in the last few years to add new languagecapabilities for advanced functional verification. I think it is time the industry considers how to make these tools easier to use by adding the necessary infrastructure of support tools.

In 2003, I expect to see the introduction of functional verification tools that make the new verification languages more accessible to designers. This past year we have seen movement toward the standardization of verification languages and the opening up of others. As a result, we are seeing more interest from hardware verification companies who want us to tailor our graphical verification product TestBencher to work with their languages and debugging environments. The industry is at a crossroads where some very interesting technologies have been developed, but the reality of learning to use the tools is a formidable barrier to being able to realize the benefits. With new graphical verification and debugging environments being released this next year, I think that we will see a significant penetration by advanced verification tools into the design flow.""

--Dan Notestein, CEO, SynaptiCAD

Synchronicity

What are the most important trends, or challenges, facing the EDA industry in 2003?

Renewed growth is dependent on the industry's end customer segment demand/growth. That will be determined by eventual migration toward more standards such as OpenAccess, OpenMORE, VSIA, and the underlying continual challenge of closing the design gap to meet the difficulties of nanometer design.

What new technologies and capabilities can EDA users expect?

While there may be some improvements in specific point tools, large development platform players making improvements to the design flows which the point tools are applied to will lead to the greatest productivity gains. These gains will be achieved by way better design standardization, reuse and reduced complexity for large SoC design.

What are your company's top priorities?

Strengthen and unify product portfolio with increased performance, scalability and functionality to overcome the ever-increasing challenges for multi-site, complex SoC development across the many design chain constituents. Deepen the penetration within our existing accounts by reaching a greater portion of the enterprise and adding new customers by demonstrating our value. Tighten our strategic relationships with the major EDA platform players.

--Mitch Mastellone, CTO, Synchronicity

Synopsys

The unification of design and verification languages will be the key challenge in 2003, with an emphasis on EDA companies delivering integrated solutions that can address the challenges of designing at 130 and 90 nanometers as designs of this complexity become more pervasive. Addressing this challenge will result in an accelerated move toward SystemVerilog, and a broader adoption of assertion-based verification. In physical design, solutions for hierarchical and virtual flat designs will become more robust.

In terms of a specific technology, signal integrity will be the most critical area to resolve in 2003. Designers must address signal integrity issues in the first pass if they don't want to incur a significant number of iterations.

Additionally, power, design for manufacture and design for test will all gain increased importance in the coming year.

Finally, open databases will become a reality in 2003, with Synopsys preparing to announce its plans for the production-proven Milkyway database in January.

With these issues in mind, new technologies will focus on dual voltage design throughout the entire flow, tighter integration and delivering solutions built around SystemVerilog.

Synopsys' top priority will be to deliver platform-based design solutions that integrate the implementation and verification tool sets and help designers resolve the signal integrity, verification, power, and design for manufacturing issues faced at 130 to 90 nm design.

--Sanjiv Kaul, senior vice president, Corporate Applications and Marketing, Synopsys, Inc.

Synplicity

The advent of next-generation cell-array architectures provides a tremendous opportunity for the EDA industry. Over the past year, ASIC design starts have decreased due to cost and time-to-market factors. Companies such as LSI Logic, NEC Electronics, AMI Semiconductor and Lightspeed have all introduced next-generation cell-array architectures to provide mid-volume customers with ASIC-like performance while reducing design risks with a silicon-proven platform. In order to enable customers to fully utilize these devices and achieve the short-turnaround times promised by the silicon vendors, the EDA industry will need to provide fast, high-performance tools that require little ramp-up time and enable designers to get their products to market quickly.

An additional challenge we see facing the EDA industry in 2003 is delivering a solution to reduce the growing complexity of verification and debug as it applies to programmable SoC (PSoC) devices. PSoC devices are attractive to both FPGA and ASIC customers. However, verifying FPGAs is now as complex as ASICs, and without a good debug methodology, customers cant take full advantage of their benefits. In order to fully utilize these devices, third-party tools and vendor-supplied debugging tools must work seamlessly together to allow designers to debug their designs from the source code. We believe easier verification and debug of PSoC devices will propel their popularity.

We also expect to see the growing adoption of some type of prototyping methodology in 2003. As the cost and complexity of ASICs continues to rise, designers will look to prototyping to functionally verify a design.

--Bernard Aronson, President and CEO, Synplicity, Inc.

Verisity

What are the most important trends, or challenges, facing the EDA industry in 2003?

Functional verification continues to be the #1 technical issue facing electronics companies today. Verification engineers are faced with thoroughly verifying increasingly more complex products in less time than ever before. In order to do this, they need new verification methodologies and technologies. Methodology is the key -- you need the best methodology and you need to make sure that your methodology will scale for the designs of tomorrow. The methodology then dictates the required technologies.

What new technologies and capabilities can EDA users expect?

Coverage-driven verification and verification reuse. Coverage-driven verification, which incorporates assertions as a key element of its methodology, is the most efficient and effective form of automating functional verification. A coverage-driven methodology allows for higher predictability, enabling engineers to capture their functional specifications and measure results with a higher rate of completeness. Coverage-driven methodologies also allow for scalability. Scalability enables engineers to verify increasingly complex systems. Verification reuse is also vital to scalability and enables an enormous increase in productivity and quality.

What are your company's top priorities?

Verisity's focus is enabling customer success through verification methodologies that focus on coverage-driven verification and verification reuse, as well as new technologies that will greatly increase the scalability of coverage-driven verification. In addition, increasing the amount and interoperability of verification components (eVCs) through expanded portfolios driven off a standard e Reuse Methodology (eRM) is a major focus for the coming year. Verisity's methodologies and technologies will enable the makers of the world's most sophisticated designs to address their most challenging business issue -- verification.

--Moshe Gavrielov, Chief Executive Officer, Verisity

Verplex Systems

I see an accelerated move toward a bottom-up assertion based verification (ABV) methodology. Designs are very complex. People do see the need to do a better job in block-level verification, so that many bugs can be taken out before system integration. This is especially important when more and more intellectual property is used in system design. Assertions can help to quickly identify and isolate the source of the problems.

Assertions are supported by formal verification tools, such as BlackTie from Verplex Systems. We also started to see simulation tools supporting assertions based on formal languages such as Sugar (or called PSL) and OVA. Users benefit by using the same specification to drive multiple tools. The Open Verification Language (OVL), which is fully compatible with the current simulation environment already, is also supported by formal tools, including BlackTie, and is gaining acceptance. There are many downloads everyday from the OVL website.

Accellera committees are also actively working on a new generation of SystemVerilog, a high-level design and verification language (HDVL). This new version of SystemVerilog will also support an assertion language that unifies common features of several other assertion languages. Such features will enable designers to specify design intent succinctly in the design process. We will see the convergence of design and verification, and a design flow that gives much more consideration to verification early in the process.

--Kuang-Chien (KC) Chen, CTO, Verplex Systems Inc.

Viasic

In the near term one big trend we see is that with the advent of physical synthesis, the hand-off point between front-end and back-end designers is changing. Front-end engineers are no longer handing off a synthesized netlist, but rather are starting to hand off a placed design. The back-end design process now starts with routing.

Signal integrity optimization needs to come together with routing at 130 nm and below. Placement will continue to merge with synthesize. Design for manufacture features will increasing be added to back-end EDA tools.

In the future, asynchronous design and other low power techniques will need to be used for battery applications. To handle larger designs look for more use of multiple CPUs and hardware acceleration of back-end EDA steps.

--Max Lloyd, CEO, Viasic

Zenasis Technologies

Key overall trends in standard cell-based integrated circuit (IC) design continue to be: (1) increasingly higher integration of functionality on a single die, (2) shrinking time to market, (3) insatiable demand for higher performance from key functional blocks like processor cores, and (4) strong preference for soft intellectual property (IP) cores over hard cores, if the soft cores can meet the desired performance targets.

Problems in meeting target performance -- for key blocks, and for the IC as a whole -- continue to have an adverse impact on design cycles for standard-cell based designs despite many advances in physical synthesis, floorplanning, and chip-level physical design solutions. Consequently, the struggle to break through 300-500 MHz clock frequencies continues for most cell-based designs.

EDA vendors are readying a mix of new tools for the coming year. Much has already been discussed about the existing and upcoming tools that allow designers to stay at high levels of abstraction. Recent advances in robust physical design estimates early in the design cycle are emerging into an extremely important category of tools. Nascent, but equally important, is the class of ""hybrid optimization"" solutions that focus on mixed cell- and transistor-level optimization of automatically created standard-cell based designs. The ability to move back and forth between cell-level and transistor-level optimization, in a seamless automated framework, opens up a new dimension in the design optimization space.

Zenasis expects to deliver the first fully integrated hybrid optimization solution to its customers in 2003.

--Debashis Bhattacharya, CTO, Zenasis Technologies Inc.

0-In Design Automation

Simulation is running out of gas. Simulation will continue to be the preferred method for confirming the design meets specified intent, but simulation alone is insufficient for eliminating implementation bugs in complex designs. Just as static timing verification and equivalence checking has replaced full-timing, gate-level simulation, a combination of assertions and formal verification will replace simulation-based, ad hoc methods for finding bugs.""

Curt Widdoes, co-founder and CTO of 0-In Design Automation