• What are the most important trends, or challenges, facing the EDA industry in 2003?
• What new technologies and capabilities can EDA users expect?
• What are your company's top priorities?

34 vendors responded, and their answers are given below, with companies listed in alphabetical order. Please scroll down to see responses from Altium, Apache Design Solutions, Applied Wave Research, Atrenta, Axis Systems, Axys Design Automation, Cadence Design Systems, CoWare, Esterel Technologies, Forte Design Systems, Get2Chip, Innologic Systems, Lisatek, Mentor Graphics, Monterey Design Automation, Nassda, Novas Software, Numerical Technologies, Oridus, Pulsic, Real Intent, Sagantec, Sequence Design, and Sigrity.

Click here to read responses from Summit Design, Synapticad, Synchronicity, Synopsys, Synplicity, Verisity, Verplex Systems, Viasic, Zenasis Technology, and 0-In Design Automation.

Altium Ltd.

What are the most important trends, or challenges, facing the EDA industry in 2003?

As the enabling software technology has matured, most of the unique performance and productivity benefits that once supported premium price positions have disappeared, and the meaningful differentiation between what were once considered "high-end" and "mainstream" tools for board design has eroded. As a result, we find that customers are increasingly concerned about both the purchase and ownership costs involved in tool selection. The emerging differences are less about tool capabilities and more about the way these tools are delivered and supported.

For the engineer the continuing challenge is still about being able to effectively and efficiently deal with the increasing complexity of circuit design. Time-to-market pressures dictated by the commercial realities of today's electronics industry mean that, while design complexity is increasing, the time available for capture, testing and prototyping is decreasing. This means that the engineer must have access to tools that facilitate all parts of the design process in unison, rather than segmenting design into discrete processes.

Also, the drive towards higher-speed systems means that the circuit, the board it sits on, and the software that runs it are more closely linked and interdependent. This means that engineers from different disciplines must work closer together than ever before to achieve a design outcome.

What new technologies and capabilities can EDA users expect?

Board-level EDA users should expect a broadening of the capabilities of their design tools, and the integration into the standard tool mix of previously expensive and restricted technologies such as simulation and signal integrity analysis. However, more than this, they should expect that these technologies will be incorporated into the standard design flow, rather than being separate processes. As an example, signal integrity should be an integral part of the capture and board layout environments.

Other technologies EDA users can expect are FPGA design capabilities added to the standard schematic editor, the expansion of component library technology to allow for multiple types of component models, and 3D board modeling built into the board layout environment.

What are your company's top priorities?

In this emerging design landscape of mixed physical and virtual components, it is becoming necessary for engineers to have access to tools that allow them to work efficiently in multiple design realms. Our priority is the creation of a single environment for capturing the multiple aspects of a modern electronics design, and one that can target multiple implementation methods. It's what we're calling Multi-Dimensional Design Capture. Simple schematic capture is no longer suitable for complex digital and processor-based systems. As well as physical circuit design, the capture environment must support the use of FPGAs as platforms for system design, and the interactive development of software to drive the system.

--Nick Martin, Founder and Joint CEO, Altium Limited

Apache Design Solutions

What are the most important trends, or challenges, facing the EDA industry in 2003?

One of the upcoming challenges for design at 130 nm and below is full-chip dynamic power integrity. This area is hard to analyze and correct, and its impact on chip timing and yield is of growing concern. Existing static analysis provides no correlation between switching events and the capacitive nature of the designs, nor does it account for high frequency inductive. As supply voltages continue to drop to 1.0 volt or less and frequencies exceed 300 MHz, identifying and avoiding dynamic power integrity issues early in the design process will be critical to SoC project success, chip yield, and ramp-to-volume.

A second important challenge for EDA will be the accurate simulation of high-speed systems such as broadband multi-gigabit I/O, Serdes, and Ethernet designs. The ability to simulate the entire path from the IC circuitry of the transceiver I/O, through the package and board parasitics, connectors, backplanes, and back again, requires a combination of frequency-domain and time-domain Spice simulation. Existing lumped-RLC approaches for modeling frequency-dependent behavior of packages, boards, and backplanes are inefficient, inaccurate, and only cover a narrow frequency band.

What new technologies and capabilities can EDA users expect?

For the successful tapeout and yield of 90 nm and high performance 130 nm designs, the issue of full-chip dynamic power and IR-drop analysis must be solved. This problem is 30 - 50 times more complex than static analysis, requiring a new approach and data handling efficiency for mixed cell-based and custom designs. It requires full-chip RLC extraction of the power/ground mesh, parasitic reduction without loss of accuracy, and transient analysis, early in the design and without requiring vectors from the designer. Users can expect to see progress in all of these areas in 2003.

Other areas that vendors will be focused on for 2003 will be in analyzing the effects and inter-dependencies of signal integrity, power integrity, and chip timing. The effect of these phenomenon on yield will be critical even for 130 nm designs, with increasing importance at the 90 nm and 65 nm nodes.

What are your company's top priorities?

Apache Design Solutions is focused on providing a comprehensive solution in the area of full-chip power integrity, I/O integrity and timing integrity for large SOCs. Our primary goal is providing fast and accurate feedback to the designer, from the early design stage through final verification, and enabling rapid "what-if" analysis in easy-to-use products.

--Andrew Yang, CEO, Apache Design Solutions

Applied Wave Research

As was accomplished on the digital side, there is a critical need to advance RF design productivity, not incrementally, but by a substantial leap. This will involve a new crop of EDA tools, better characterized libraries, and a fresh look at the disjointed and ineffective design methodologies that exist today. As is the case in digital design "timing closure," a much tighter integration of the RF system and circuit design process is required for more rapid "requirements closure." This coupled with the unification of the electrical and physical design process will assure better "performance closure."

Today's popular RF design tools and their integration have evolved haphazardly with different databases, GUIs, and translators. Though they grudgingly get the job done, their legacy offers little hope for meaningful productivity improvements. One of AWR's top priorities in 2003 is to deliver EDA tools that are seamlessly integrated through an architecture and unified database designed for RF with a consistent interface.

To handle the increasing complexity and more demanding performance requirements of RF transceivers, AWR is also planning a number of design tool advances. These will include greater capacity system and circuit simulators using more accurate/efficient non-linear and passive models to predict more complex product requirements. To improve "requirements closure," our system simulator will comprehend the non-ideal RF impairment of the circuit components and their impedance mismatch fast enough to deal with complex digital modulation schemes in real-time. In order to accelerate "performance closure," our circuit simulators will comprehend physical parasitics as the layout is progressing.

Finally, there is a crying need for better foundry and component libraries for RF design. At the circuit level, design kits, sometimes referred to as PDKs, have emerged for many of the commercial foundries. Analogous to standard cell libraries for digital design, these PDKs form the foundation for qualified circuit design sign-off. They are acceptable for low-frequency applications, but are grossly inadequate for the RF space. AWR is investing heavily in both RF PDKs and components libraries for the major foundries and wireless standards.

--James Spoto, President and CEO, Applied Wave Research, Inc.

Atrenta

What are the most important trends, or challenges, facing the EDA industry in 2003?

The ability to design SoCs in a cost effective and timely manner continues to be a major challenge for the industry. The use of standards and consistent design techniques, early visibility into integration issues and the use of proper planning tools are critical for success. The alternatives, which include a brute force approach with multiple parallel teams, significant iterations and a massive communication infrastructure often spread across the globe, are both unaffordable and unmanageable.

The time and cost of iterations are increasing. We have to be able to use predictive analysis to catch design and integration problems early at RTL. Customers can't keep looping back to fix bugs that should have been caught at RTL or they'll miss important deadlines.

What new technologies and capabilities can EDA users expect?

Customers want and need a unified solution that does multi-domain analysis and optimization. Power, area and timing need to be analyzed and optimized at the same time, not independently, because what optimizes power, for example, may increase area and slow timing. This analysis and optimization needs to be done up-front at RTL for the smoothest, fastest possible design flow. Changes made later in the design cycle make IP reuse difficult if not impossible.

What are your company's top priorities?

Our top priority is to strengthen our predictive analysis technology for logical virtual prototyping. Predictive analysis has been widely accepted by our customers, and we need to keep adding new capabilities so we can reach that holy grail of multi-domain optimization at RTL.

--Ajoy Bose, President and CEO, Atrenta

Axis Systems

Design has long been the major cost center for any electronic product. Up to 90 percent of any given product's price is spent on the design, and verification can represent as much as 70 percent of the design cost. The conventional wisdom on the verification of system-on-chip designs is that it can never be finished because the time spent on verification expands according to whatever time there is available. Therefore the cost of verification is as infinite as the process.

But that is not the time we live in today. The suppliers of verification technology must not only define the limits they must find a way to find a way to shorten the process and, thereby, reduce the overall cost of verification in the design process.

I believe there is a definable limit to what it takes to accurately verify a design and that the cost of verifying the design can be dramatically reduced.

--Steve Wang, cofounder and VP of marketing, Axis Systems

Axys Design Automation

The year 2003 may well turn out to be a pivotal year for system-level design. It likely will set the direction as to whether or not EDA vendors will participate in this area in the long run, and maintain a stake in early product differentiation.

If EDA does not address the technology challenges and business aspects of embedded software and system-level design, then it is at serious risk of becoming an electronic design commodity. It will remain a necessary part of the product design, but CEOs of consumer companies will not be losing sleep at night over EDA issues. They worry whether the products meet the system-level target requirements and about rolling out embedded software at appropriate cost with lesser bugs. Solutions to these challenges will be sourced from the embedded software and system-level design world.

Axys Design will continue to focus on market leading, fast C++ and SystemC based processor modeling and SoC simulation. The market for system-level virtual prototypes will be ready to grow from pure hardware-aware embedded software design into the application software development space.

--Frank Schirrmeister, vice president of business development, Axys Design Automation

Cadence Design Systems

Design customers are struggling with challenges in performance, capacity, and cost. These are distilling out as cost issues in this down economy. On the technological side, customers were surprised at the manufacturability problems at 130 nanometers, and they are dreading them at 90 nanometers, especially since their resources to attack the problems are now limited. And, of course, the design and manufacturing realms are becoming increasingly interdependent at smaller geometries.

Cadence's priorities are to improve the profitability of semiconductor companies with technologies that support their product development efforts -- getting chips out and yields up; drive nanometer design tools into interoperable systems; increase customer satisfaction with products, services and support; and help restore growth to the electronic design industry as a whole.

Users will start the new year with true IC design tool interoperability through the OpenAccess database and API. OpenAccess will help electronics companies more quickly and easily create integrated design flows of tools from multiple vendors and internal technology. In December 2002, Cadence delivered the source code to the OpenAccess Coalition. In January 2003, the Coalition expects to make the database source code freely available to design engineers worldwide through its open-community source program via OpenEDA.org.

Verification
Verification continues to be an enormous challenge for designers. It is well known that verification consumes more than 70 percent of the design cycle. EDA users face a daunting range of challenges, including system, testbench and design language selection; efficient testbench development; functional coverage; verification IP and reuse; massive digital verification; advanced verification techniques; hardware/software co-verification; and mixed-signal verification.

Cadence will provide new technologies and methodologies to address these issues. Our top priority in this area is to increase the speed and efficiency of the overall verification process.

Digital ICs
Designers' challenges in advanced technologies have been exacerbated by wire effects, such as signal integrity and power-related problems, which can make or break a chip. Designers who don't use a wire-centric methodology will be at a severe disadvantage. The Cadence Encounter platform provides a continuous convergence methodology that allows design teams to achieve predictable, systematic progress every single day.

Custom - Analog/Mixed Signal
The biggest hurdle for most of our customers is mask cost and low yield in the 130nm and 90nm process technologies. EDA providers have to work more closely with chip designers and silicon providers, for example, foundries and IP vendors. Other customer challenges include mixed-signal design simulation and verification, ramping 90nm designs, and putting together large chips with place and route and custom blocks.

System-Package-Board
PCB design today is all about speed: device speed, system speed and time to market. We will see adoption of new design methodologies that allow for the co-design of the silicon, the package and the board. For example, Cadence will introduce technology in 2003 that will revolutionize co-design, providing chip I/O planning capability and addressing packaging far earlier in the design process than ever before. In the networking area, the challenge is differential signal technology, which drives large amounts of data over long distances. New EDA technology will speed design, analysis and implementation at the signal analysis and routing design stages.

--Ray Bingham, CEO, Cadence Design Systems

CoWare

In 2003, the trend towards platform-based design accelerates due to relentless cost reduction, short market windows, and increasing chip complexity. Successful companies will also want to maximize the number of end products derived from each platform. Getting the right architecture to meet these needs becomes a dominant design challenge. How much processor power is required? Which bus to use? What specialized processing is needed? How much functionality should be in software?

It's not about simply getting the maximum clock speed and reaching timing closure anymore. The new challenges in EDA center around helping customers create the optimal system design, without under- (or equally important today, over-) engineering the product.

--Mark Milligan, vice president of marketing, CoWare, Inc.

Esterel Technologies

What are the most important trends, or challenges, facing the EDA industry in 2003?

The biggest challenge remains delivering on our promise to create cost effective design and verification solutions capable of handling 10 million+ gate designs with multiple processors, a growing amount of embedded software and ever shortening time to market windows.

Users need powerful system and software modeling environments that integrate design and early automated verification. We will never solve the verification bottleneck with only a separate step called "verification" acting on final netlist or code, where the structure and logic of a design is buried under low-level details. Also, since users will always enhance their flow with new best of class point tools all serious EDA tools must be created with an architecture that allows easy integration into existing environments and tools.

What new technologies and capabilities can EDA users expect?

A new generation of system level and module level design and verification tools will begin to proliferate during 2003. These new and enhanced solutions will be capable of handling both control and data flow with equal ability in a single environment. Due to their exceptionally strong mathematical base, the most sophisticated of these tools will create designs that are "correct by construction," substantially reducing the verification task.

What are your company's top priorities?

Esterel Technologies SCADE suite product is virtually a de-facto standard in Europe for the creation of safety critical embedded software for Civilian Avionics, and an emerging standard for these types of applications in the automotive industry. Within the last few months we have begun to introduce these products in the U.S. Completing this introduction is a top 2003 priority for us.

By mid 2003 our new generation of Esterel Studio, Esterel Studio 5.0, will move beyond its current use by early adopters and become available to the general market. Esterel Studio 5.0 will provide users with high-level design, verification, and synthesis of circuits.

--Eric Bantegnie, CEO, Esterel Technologies

Forte Design Systems

What are the most important trends, or challenges, facing the EDA industry in 2003?

The most important trend for next year will continue to be the push towards design and verification at "higher levels of abstraction." While the phrase has been somewhat abused in the last two years, clarification is coming through continued design successes with new methodologies. In 2003 these success stories will convincingly demonstrate what is achievable. Raising the abstraction level for hardware and system-level design will be the single largest contributor to engineering productivity gains over the next 2-3 years. These new methodologies will allow design complexity to increase at a much more rapid pace than over the past several years.

What new technologies and capabilities can EDA users expect?

In the next 12 months, EDA users can expect continued deployment of methodologies and technologies that will positively affect stagnating design productivity levels. We expect a number of success stories showing significant productivity gains derived from next generation behavioral and architectural synthesis technologies. This will drive design teams to deploy "behavioral design" in many application spaces. By allowing the lines to be blurred between design and verification, SystemC and behavioral design will grow to play a significant role in the definition of complex ASICs and SoCs. This methodology will then allow functional design and verification to happen earlier in the process, diminishing the role of traditional verification, and thus further increasing productivity while increasing probability of design first time success.

What are your company's top priorities?

Forte Design Systems' top priority is the continuous focus on our customers' success. We do this by creating and marketing innovative new technologies that significantly enhance design and verification productivity, especially for SoC and ASIC designs with gate counts above one million.

--Jacob Jacobsson, President and CEO, Forte Design Systems

Get2 Chip

In 2003, we will see the maturation of the physical convergence tools and the expectations surrounding them. The hype or dream of physical synthesis with push button operation from RTL to GDSII will face the dark reality of infeasibility. It will become clear that a "new front end" has emerged. This emergence will be driven by the complexity and physics of .13-micron and below process technology. A new generation of global RTL synthesis optimization for design closure with massive capacity and superior quality of results will be recognized as the centerpiece technology for this new front end.

Architectural synthesis will gain the attention of the market once again as the daunting complexity of 100M-gate designs in 90nm design projects are planned and undertaken. Manpower cannot continue to be scaled up to meet the raw complexity challenge; abstraction is the only realistic hope for the not-so-distant realm of 1-billion gate design.

Finally, a new wave of EDA startups will be born out of the opportunities resulting from the Synopsys-Avant! merger. Missteps, product overlap and attrition will be shown to be the catalyst for this new wave of new technology startups.

--Chi-Ping Hsu, COO, Get2Chip Inc.

Innologic Systems

One of the most important trends facing the EDA industry is the verification challenge being created by 90nm and below process technologies, and gigabit and beyond performance requirements. The combination of these two dynamics results in an increasing amount of SOC real estate being devoted to custom silicon implementations, especially in the areas of memory and I/O.

The increasingly complex functionality being incorporated into virtually all communication products, from the "big iron" routers used by telcos to desktop PCs and handheld mobile devices, require the use of full custom design techniques. While formal verification methodologies have traditionally been applied to ASIC flows, the same kind of formal verification practices must also be applied at the circuit level. For custom silicon elements "good enough" design practices cannot ensure adequate verification coverage.

Formal verification is the only effective means to achieve 100 percent functional verification coverage to eliminate potential product-killing bugs. For full custom designs, there is a need for a technology that enables behavioral models to be compared against spice-level netlists -- in essence, a formal verification solution that allows customers to achieve a higher level of confidence that the custom silicon elements within their products will work as designed and verified.

At Innologic, we have learned that "custom" becomes the operative term for formal verification of these memory and specialty I/O elements that are very application specific. On the memory side, verifying a Flash implementation is different than verifying a DRAM implementation. On the I/O side, applications such as serial ATA and Hyper-Transport all require a "custom" approach in terms of formal verification.

As a result of the forgoing, Innologic's focus for 2003 will be to continually enhance our existing technology and solutions and work with our customers to address the application-specific formal verification requirements of their custom silicon implementations.

--Dian Yang, president and CEO, Innologic Systems, Inc.

LISAtek

What are the most important trends or challenges facing the EDA industry in 2003?

Reducing the cost of hardware and embedded software design is the top challenge. Increased integration densities and multiple programmable cores in SoC designs call for greater design efficiency, and tools that automate more of the design process. These tools must be integrated and complete in their support of HW/SW co-design and system-level HW/SW simulation and verification.

What new technologies and capabilities can EDA users expect?

Integrated, automated tools with the power to handle complex SoC and embedded system design. Margins are declining while the costs of verification and IP are high. By using integrated tools to automatically define, simulate, and optimize embedded cores and embedded application software, chip companies can eliminate IP royalties, increase product margins, and get to market sooner.

What are your company's top priorities?

Driving faster time-to-market and increasing margins for our customers. By automating HW/SW co-design with our integrated tools, designers can perform architecture exploration, optimization, and early system-level verification faster than ever before, and at a lower cost. They can develop architecture and embedded software in parallel, analyze system bottlenecks, and optimize HW and SW designs -- all before any HDL code is generated. And, LISATek's tools are integrated with CoCentric, CoWare, and Seamless to link embedded core design with system-level design and verification.

--Uri Myer, President, LISATek

Mentor Graphics

Overall, we see 2003 as being a better year for the industry, but still challenging. 2003 will see increasing pressure at both the high and low ends. The 'Wal-Mart' phenomenon will drive design teams to get very cost conscious to stay competitive. Companies just won't be able to pay for $20 million SoC designs before they see first silicon. Managing cost will go hand in hand with managing risk, and system verification technologies will play an increasing role. Various forms of virtual prototyping, and system-level simulation will become more critical.

At the high-end, the continuous push to 0.13m and beginning .09m will put physical verification and analysis in the spotlight. Resolution enhancement technology will move out of the lab and into production as new designs require it. Design for manufacturability tools will become increasingly important as designers turn to software to help solve yield problems. Design for test, in particular, will be under pressure as test patterns volume will rise to accommodate new fault models that arise at smaller geometries.

At the lower-end of design, programmable logic will continue its trend of taking more and more of the total design starts. Designer concerns about performance, power, and functionality will continue to fade as the technology gap closes. Better integration into system design environments will make programmable logic a preferred platform when time-to-market is an issue.

Mentor's priorities will be: 1) Staying ahead of the nanometer technology curve with new Calibre-based physical verification, analysis and reticule enhancement technologies and products, 2) Enhancing field programmable logic tools to achieve highest performance, ease of use and embedded IP capability, and 3) Expanding the ultra-low cost tools available to system designers doing PCBs and programmable logic.

--Walden C. Rhines, Chairman and CEO, Mentor Graphics

Monterey Design Automation

What are the most important trends, or challenges, facing the EDA industry in 2003?

In 2002, design planning was a hot area as evidenced by the introduction of new products and acquisitions. In 2003, design planning will continue to evolve beyond rudimentary gate-level partitioning and placement to higher levels of physical abstraction to handle complex SoC designs composed of hundreds of hard macros and millions of gates. Design planners must be able to deal with entire sub-systems as design objects and manage complex hierarchical structures automatically. Only by rising above the gate level can design planners meet the challenges posed by multi-million gate nanometer chips.

Prototyping really caught fire in 2002 and we believe that this trend will continue in 2003 as more and more chip designers seek early feedback on the achievability of the final implementation. However, some prototyping tools take an overly simplistic approach by performing a fast placement and crude, DRC-incorrect detailed route that bears no resemblance to the final layout, even to the extent of ignoring such critical aspects as power and clock nets. Prototyping is only useful if it: 1) delivers an accurate physical prototype that correlates closely to the final implementation, 2) takes into account the physical effects of power and clock networks, 3) can handle multi-million gate chips in several hours, and 4) works together with the chip-level design planner on hierarchical designs containing hundreds of large blocks.

In the area of physical implementation, vendors are converging on an approach that optimizes all design parameters simultaneously. In reality, most of these offerings continue to employ a haphazard, sequential construct-analyze-repair approach that requires a rocket scientist and a brain surgeon to achieve design closure. Only a solution that has been architected from the ground up to consider all design parameters simultaneously can hope to achieve total design closure on multi-million gate nanometer designs.

What new technologies and capabilities can EDA users expect?

An exciting area will be the convergence of the physical front-end where chip designers can perform planning and prototyping in a single integrated environment. We see this as the most significant opportunity for development in 2003.

What are your company's top priorities?

Our top priority is the same in 2003 as it has always been -- to deliver outstanding value to our customers beyond what they can procure from any other vendor. To work with them as partners such that our respective goals are in alignment, rather than at odds with them, as has defined the EDA vendor-customer relationship in the past.

--Jacques Benkoski, President and CEO, Monterey Design Systems

Nassda

The IC design automation industry will have a challenging 2003 as the semiconductor industry continues to recover from the downturn. Tool budgets in the industry are still under very tight scrutiny. The opportunity in front of the industry is to provide design tools that meet the demands of nanometer-scale ICs reaching down to 90nm.

Full-chip post-layout analysis for timing, power, signal integrity, and IR drop effects will become even more vital, since the pressure for early silicon success and quicker time-to-profit continues to build. Being able to verify big analog/mixed-signal components with big digital-only blocks is still not a mature capability available to designers, and still needs further development.

We see the need for better reliability analysis to handle effects such as NBTI and HCI, which threaten to reduce both product yield and lifetime.

We also see that high performance digital-only designs running over 500MHz or in 130nm processes need transistor-level verification of their critical paths and clock networks. The increase in the number of re-spins at 130nm shows that static timing analysis in the digital design flow does have the accuracy necessary to provide timing signoff for these nanometer designs.

--Sang Wang, CEO, Nassda

Novas Software

What are the most important trends, or challenges, facing the EDA industry in 2003?

The key challenge remains customer budgets. Is the semiconductor market really at bottom and starting to grow, or is it still wishful thinking? How long will the R&D investment cycle lag renewed growth in sales, and how broad will the recovery be? It could be a real challenge if there's a narrow recovery, with only a few companies starting to renew their investment priorities.

A key trend, and another challenge, is the transition to assertion-based verification. I expect practical applications to emerge, but there are still standardization hurdles to overcome, and industry infighting about languages remains a risk. The work of the Acellera committees to carve out a rational assertions subset is encouraging, but it really needs to stay on track and produce an efficient spec by the June Design Automation Conference.

What new technologies and capabilities can EDA users expect?

Elaborating on the trend toward assertion-based verification, we'll see simulation-based engines that make use of assertions, as well as refinements to formal tools. Gradually, users will start actually writing assertions. They'll continue to be interested in pre-packaged assertions too. It's going to take a combination of success with pre-packaged assertions; effective engines that use assertions, and standard languages to get people to really embrace the concept. I expect 2003 to be a pivotal year for this.

Users can expect a lot of hype about assertions, and they're going to have to be careful to separate the wheat from the chaff. There will be some truly powerful applications, but there will be a lot of unfulfilled claims too.

What are your company's top priorities?

Our top priority is to take care of our customers. They're going through their toughest times ever, and we intend to keep supporting them and working with them to help them get their chips out the door so they can be as competitive as possible. After that, our focus is on refining our latest products and continuing to develop the new technologies that will keep moving our customers' productivity forward.

Keeping pace with the rapidly changing verification environment takes considerable time, talent, and dedication. We're going to be there with debug solutions for testbench languages, System Verilog, and assertion languages, and systems that integrate with the emerging engines. Our vision is to provide a seamless user experience across languages and tools as the verification methodology evolves.

--Scott Sandler, president and CEO

Numerical Technologies

What are the most important trends, or challenges, facing the EDA industry in 2003?

In 2003, design-for-manufacturability -- a buzzword for many years -- will have new meaning for designers whose world has evolved to include subwavelength feature sizes, new materials, various resolution enhancement techniques, more intricate photomasks, creative lithography strategies, and exploding data volumes.

Given this environment, three equally significant challenges face the EDA industry: smaller geometries, increasing complexity, and semiconductor industry dis-aggregation.

What new technologies and capabilities can EDA users expect?

We can expect to see further innovation in subwavelength lithography-enabling technologies such as optical proximity correction (OPC) and phase-shifting masks (PSM). With subwavelength geometries, smarter choices upstream will enable the engineers down the line to handle complexity easily and efficiently. Moving manufacturing decisions up front in the design phase will become critical, and we can expect tools that deliver dramatic increases in throughput by allowing designers to confidently make modifications that correct for process variations.

But we can't expect to hold designers accountable for critical mask and process decisions anytime soon, and manufacturing is already burdened with yield and other issues. There is a huge opportunity in 2003 for a new wave of design-to-silicon specialists who truly understand the specific pitfalls encountered during the handoff of advanced designs to manufacturing, and who are now positioned to provide solutions that empower both sides to focus on what they do best. In short, look for design tools that automate the use and application of OPC and PSM methodologies, obviating the need for designers to become process experts and vice versa.

In terms of managing complexity, process-smart EDA tools will be key, as well as tools that effectively pass on more design intelligence to manufacturing. Initiatives like OpenAccess are steps in the right direction, since reading off a coherent database will allow the industry to manage data and complexity a whole lot better. The design community needs to realize that the data explosion is fast becoming a hurdle that is as critical as the SoC complexity problem.

In the recent past, experts put forward cogent arguments about the need to tie design tools to silicon, but at the same time the industry kept moving ahead with independent design tools. Intelligent choices need to be made at every step since "process-inept" designs will create hell for the mask maker. These discontinuities in the design-to-silicon chain could obsolete many EDA tools in the worst case, especially if they become totally dissociated with the realities of silicon manufacturing. At a high level, the EDA companies have realized this need to "re-aggregate" in order to keep up with the process changes and the subwavelength impact.

Re-aggregation of information is going to be the real challenge. Expect to see a growing trend towards intelligent partnering in order to effectively address the finer geometries and complexity challenges moving ahead.

What are your company's top priorities?

Numerical will address these challenges by:

• Continuing to facilitate the industry's eventual move to volume 130-nm design and manufacturing.
• Developing industry-wide solutions to the growing data explosion at 130-nm and smaller process generations.
• Ensuring that manufacturing issues are dealt with transparently throughout the design flow.

--Atul Sharan, senior VP of worldwide sales and marketing, Numerical Technologies

Oridus

What are the most important trends, or challenges, facing the EDA industry in 2003?

Communication from design to manufacture. With design teams and fabs spread around the world, and EDA tools and ICs becoming more complex, design teams will have to adopt new ways of communicating to avoid confusion and costly mistakes in the development of next generation devices.

In the past, designers only had to deal with the front-end of the design process and achieving timing closure. But, engineers can no longer design just to spec. To reach production, design teams need to understand the entire design and process tradeoffs. Fabrication and test rules must factor into the equation. Mask and fab teams need to be in daily contact to exchange information.

Leveraging the Internet's capabilities will be a key trend in 2003. You will see more announcements from EDA, semiconductor, foundry and testing houses deploying Web communication infrastructures. Communication will evolve from linear communication, one to one, to near real-time communication, many to many, using the Internet.

What new technologies and capabilities can EDA users expect?

Web solutions that are easy to use, maintain, and provide a server-based model to maintain IP security. Web communication will evolve to include robust voice, as well as data capability. Oridus' current record/replay features can capture the design sequences and archive the material providing a documented history of the design process for optimum communication.

What are your company's top priorities?

The top priorities for Oridus over the next 12 months will be to increase the usability and scalability of its products. In addition, the company will partner to integrate its technology into software and database vendor products for an overall embedded Internet solution.

--Kuo-Chun Lee, President and CEO, Oridus Inc.

Pulsic Ltd.

What are the most important trends, or challenges, facing the EDA industry in 2003?

It is now evident that the mainstream arrival of process sizes of 0.13 microns and below has delivered a new set of physical problems for IC designers -- meeting timing and signal-integrity constraints in the interconnect while still maintaining DRC correct wiring, controlling power consumption, die-size and time to market.

Timing and signal-integrity issues prior to the deep sub-micron era were traditionally considered as second order effects, but these are now effectively first order effects. Interconnect delay is the major contributory factor to these issues, caused by the vast number of ever finer wires having less space between them -- thus causing cross capacitive coupling. These wiring problems pose the biggest challenge in IC physical design today, and as smaller process geometries of 90nm and beyond come into play, this is set to get even worse.

What new technologies and capabilities can EDA users expect?

We have seen EDA solutions emerging through last year that attempt to target the resolution of these wiring related problems. For the most part, they offer an early "heads-up" to these problems by way of a Silicon Virtual Prototype (SVP). This approach basically uses a gridded, or pseudo-gridded, routing engine to get the wiring down as fast as possible -- ignoring DRC violations -- so that a more realistic analysis of these problems can be performed due to the actual wiring being present. This result then gets continually refined over many iterations.

The inherent problem with this approach is the fact that the wiring is not DRC correct -- and so by the time the timing and signal-integrity issues have hopefully been resolved, and the wiring achieves 100% completion with no DRC violations, this can be a very long way down the iteration path. However, this solution has received much attention through the latter half of 2002 and EDA users can no doubt expect to see more of the same through 2003.

What are your company's top priorities?

2003 will be both an exciting and challenging year for Pulsic as an EDA startup during this extremely difficult time for the industry. We plan to move forward by using a very strategic approach in terms of technology focus, recruitment of the best people and development of commercial partnerships and key customer accounts.

--Mark Williams, CEO, Pulsic Ltd.

Real Intent

Design verification will be the clear focus of the EDA industry in 2003. There will be a shift from the focus on physical design. Automatic formal analysis and Assertion-Based Verification (ABV) will become an integral part of mainstream verification methodology.

Powerful solutions based on automatic formal analysis are already available. These include Implied Intent and Clock Intent Analysis in Real Intent's Verix. 2003 will see a launch of many more such capabilities.

The emerging SystemVerilog standard from Accellera will propel Assertion-Based Verification. Standardization coupled with advances in tool capacity and performance will make this methodology mainstream.

Real Intent will continue to support the Accellera standardization process and will lead the emergence of the Assertion Based Verification methodologies.

-Prakash Narain, CEO, Real Intent

Sagantec

The latest nanometer designs and process technologies are stressing existing design tools and methodologies. The effects of the increased complexity are felt most severely in the area of analog physical design -- to this day a largely manual task. Demand for tools to automate analog/mixed-signal physical design will only increase as nanometer processes are used to implement higher levels of integration on a single chip, thus ensuring some analog and mixed-signal design on almost every chip. Automation of analog/mixed signal design is also critical to analog design reuse -a practice that will speed new products to market and simplify process migration and changing foundries.

Many high volume products are fabricated at less than optimal yield. Improving the yield can save hundreds of millions of dollars for semiconductor companies. There is a need for safe and verifiable design manipulation that improves yield by a significant and measurable amount with minimal impact on schedule. Automation of physical design correction and optimization is one effective means of addressing this need.

--Coby Zelnik, Sr. VP of Business Development, Sagantec

Sequence Design

What are the most important trends, or challenges, facing the EDA industry in 2003?

Power -- Who invited this guy? Just when we thought we had it all figured out and could deal with timing, signal-integrity, and area, along came power with its uncanny knack for screwing up all the things we thought we understood and dropping a few new ones on us at the same time.

What new technologies and capabilities can EDA users expect?

Since users also recognize power as the top design challenge, expect to see a great deal of activity on this front. The holy grail is a complete, predictable, and automated power reduction flow.

What are your company's top priorities?

We will be honing our NanoCool flow to span the design space from architectural design to RTL down to the physical level. At higher levels, low-power design methods reduce wasted power and explore the design space to produce the lowest-power architecture. Simultaneously, designers must have a good prediction of the power savings accruing through automatic structural power optimization at the physical level.

As we move to smaller geometries, interconnect effects will dominate. It will be crucial for EDA companies to work closely with semiconductor foundries to make low-power, low-voltage designs a reality. Optimization at the physical level for power consumption must be done concurrently with timing and signal integrity. Finally, power integrity will be a wild card. This power-driven flow must be supported by high-capacity, fast, and accurate power analysis at all levels of abstraction.

--Vic Kulkarni, President and CEO, Sequence Design

Sigrity

An increasingly significant challenge that stands out in the design of high-speed electronic products is the capability of fast and accurate dynamic analysis of power delivery systems. This includes power delivery systems on chip, on package and on board. The system level analysis capability of the entire power delivery system enables the optimization of total system performance. Sigrity's top priority in year 2003 is to bring this capability to the marketplace.

--Jiayuan Fang, President, Sigrity, Inc.

SynaptiCAD

There's been a lot of effort in the last few years to add new languagecapabilities for advanced functional verification. I think it is time the industry considers how to make these tools easier to use by adding the necessary infrastructure of support tools.

In 2003, I expect to see the introduction of functional verification tools that make the new verification languages more accessible to designers. This past year we have seen movement toward the standardization of verification languages and the opening up of others. As a result, we are seeing more interest from hardware verification companies who want us to tailor our graphical verification product TestBencher to work with their languages and debugging environments. The industry is at a crossroads where some very interesting technologies have been developed, but the reality of learning to use the tools is a formidable barrier to being able to realize the benefits. With new graphical verification and debugging environments being released this next year, I think that we will see a significant penetration by advanced verification tools into the design flow.""

--Dan Notestein, CEO, SynaptiCAD

Synchronicity

What are the most important trends, or challenges, facing the EDA industry in 2003?

Renewed growth is dependent on the industry's end customer segment demand/growth. That will be determined by eventual migration toward more standards such as OpenAccess, OpenMORE, VSIA, and the underlying continual challenge of closing the design gap to meet the difficulties of nanometer design.

What new technologies and capabilities can EDA users expect?

While there may be some improvements in specific point tools, large development platform players making improvements to the design flows which the point tools are applied to will lead to the greatest productivity gains. These gains will be achieved by way better design standardization, reuse and reduced complexity for large SoC design.

What are your company's top priorities?

Strengthen and unify product portfolio with increased performance, scalability and functionality to overcome the ever-increasing challenges for multi-site, complex SoC development across the many design chain constituents. Deepen the penetration within our existing accounts by reaching a greater portion of the enterprise and adding new customers by demonstrating our value. Tighten our strategic relationships with the major EDA platform players.

--Mitch Mastellone, CTO, Synchronicity

Synopsys

The unification of design and verification languages will be the key challenge in 2003, with an emphasis on EDA companies delivering integrated solutions that can address the challenges of designing at 130 and 90 nanometers as designs of this complexity become more pervasive. Addressing this challenge will result in an accelerated move toward SystemVerilog, and a broader adoption of assertion-based verification. In physical design, solutions for hierarchical and virtual flat designs will become more robust.

In terms of a specific technology, signal integrity will be the most critical area to resolve in 2003. Designers must address signal integrity issues in the first pass if they don't want to incur a significant number of iterations.

Additionally, power, design for manufacture and design for test will all gain increased importance in the coming year.

Finally, open databases will become a reality in 2003, with Synopsys preparing to announce its plans for the production-proven Milkyway database in January.

With these issues in mind, new technologies will focus on dual voltage design throughout the entire flow, tighter integration and delivering solutions built around SystemVerilog.

Synopsys' top priority will be to deliver platform-based design solutions that integrate the implementation and verification tool sets and help designers resolve the signal integrity, verification, power, and design for manufacturing issues faced at 130 to 90 nm design.

--Sanjiv Kaul, senior vice president, Corporate Applications and Marketing, Synopsys, Inc.

Synplicity

The advent of next-generation cell-array architectures provides a tremendous opportunity for the EDA industry. Over the past year, ASIC design starts have decreased due to cost and time-to-market factors. Companies such as LSI Logic, NEC Electronics, AMI Semiconductor and Lightspeed have all introduced next-generation cell-array architectures to provide mid-volume customers with ASIC-like performance while reducing design risks with a silicon-proven platform. In order to enable customers to fully utilize these devices and achieve the short-turnaround times promised by the silicon vendors, the EDA industry will need to provide fast, high-performance tools that require little ramp-up time and enable designers to get their products to market quickly.

An additional challenge we see facing the EDA industry in 2003 is delivering a solution to reduce the growing complexity of verification and debug as it applies to programmable SoC (PSoC) devices. PSoC devices are attractive to both FPGA and ASIC customers. However, verifying FPGAs is now as complex as ASICs, and without a good debug methodology, customers cant take full advantage of their benefits. In order to fully utilize these devices, third-party tools and vendor-supplied debugging tools must work seamlessly together to allow designers to debug their designs from the source code. We believe easier verification and debug of PSoC devices will propel their popularity.

We also expect to see the growing adoption of some type of prototyping methodology in 2003. As the cost and complexity of ASICs continues to rise, designers will look to prototyping to functionally verify a design.

--Bernard Aronson, President and CEO, Synplicity, Inc.

Verisity

What are the most important trends, or challenges, facing the EDA industry in 2003?

Functional verification continues to be the #1 technical issue facing electronics companies today. Verification engineers are faced with thoroughly verifying increasingly more complex products in less time than ever before. In order to do this, they need new verification methodologies and technologies. Methodology is the key -- you need the best methodology and you need to make sure that your methodology will scale for the designs of tomorrow. The methodology then dictates the required technologies.

What new technologies and capabilities can EDA users expect?

Coverage-driven verification and verification reuse. Coverage-driven verification, which incorporates assertions as a key element of its methodology, is the most efficient and effective form of automating functional verification. A coverage-driven methodology allows for higher predictability, enabling engineers to capture their functional specifications and measure results with a higher rate of completeness. Coverage-driven methodologies also allow for scalability. Scalability enables engineers to verify increasingly complex systems. Verification reuse is also vital to scalability and enables an enormous increase in productivity and quality.

What are your company's top priorities?

Verisity's focus is enabling customer success through verification methodologies that focus on coverage-driven verification and verification reuse, as well as new technologies that will greatly increase the scalability of coverage-driven verification. In addition, increasing the amount and interoperability of verification components (eVCs) through expanded portfolios driven off a standard e Reuse Methodology (eRM) is a major focus for the coming year. Verisity's methodologies and technologies will enable the makers of the world's most sophisticated designs to address their most challenging business issue -- verification.

--Moshe Gavrielov, Chief Executive Officer, Verisity

Verplex Systems

I see an accelerated move toward a bottom-up assertion based verification (ABV) methodology. Designs are very complex. People do see the need to do a better job in block-level verification, so that many bugs can be taken out before system integration. This is especially important when more and more intellectual property is used in system design. Assertions can help to quickly identify and isolate the source of the problems.

Assertions are supported by formal verification tools, such as BlackTie from Verplex Systems. We also started to see simulation tools supporting assertions based on formal languages such as Sugar (or called PSL) and OVA. Users benefit by using the same specification to drive multiple tools. The Open Verification Language (OVL), which is fully compatible with the current simulation environment already, is also supported by formal tools, including BlackTie, and is gaining acceptance. There are many downloads everyday from the OVL website.

Accellera committees are also actively working on a new generation of SystemVerilog, a high-level design and verification language (HDVL). This new version of SystemVerilog will also support an assertion language that unifies common features of several other assertion languages. Such features will enable designers to specify design intent succinctly in the design process. We will see the convergence of design and verification, and a design flow that gives much more consideration to verification early in the process.

--Kuang-Chien (KC) Chen, CTO, Verplex Systems Inc.

Viasic

In the near term one big trend we see is that with the advent of physical synthesis, the hand-off point between front-end and back-end designers is changing. Front-end engineers are no longer handing off a synthesized netlist, but rather are starting to hand off a placed design. The back-end design process now starts with routing.

Signal integrity optimization needs to come together with routing at 130 nm and below. Placement will continue to merge with synthesize. Design for manufacture features will increasing be added to back-end EDA tools.

In the future, asynchronous design and other low power techniques will need to be used for battery applications. To handle larger designs look for more use of multiple CPUs and hardware acceleration of back-end EDA steps.

--Max Lloyd, CEO, Viasic

Zenasis Technologies

Key overall trends in standard cell-based integrated circuit (IC) design continue to be: (1) increasingly higher integration of functionality on a single die, (2) shrinking time to market, (3) insatiable demand for higher performance from key functional blocks like processor cores, and (4) strong preference for soft intellectual property (IP) cores over hard cores, if the soft cores can meet the desired performance targets.

Problems in meeting target performance -- for key blocks, and for the IC as a whole -- continue to have an adverse impact on design cycles for standard-cell based designs despite many advances in physical synthesis, floorplanning, and chip-level physical design solutions. Consequently, the struggle to break through 300-500 MHz clock frequencies continues for most cell-based designs.

EDA vendors are readying a mix of new tools for the coming year. Much has already been discussed about the existing and upcoming tools that allow designers to stay at high levels of abstraction. Recent advances in robust physical design estimates early in the design cycle are emerging into an extremely important category of tools. Nascent, but equally important, is the class of ""hybrid optimization"" solutions that focus on mixed cell- and transistor-level optimization of automatically created standard-cell based designs. The ability to move back and forth between cell-level and transistor-level optimization, in a seamless automated framework, opens up a new dimension in the design optimization space.

Zenasis expects to deliver the first fully integrated hybrid optimization solution to its customers in 2003.

--Debashis Bhattacharya, CTO, Zenasis Technologies Inc.

0-In Design Automation

Simulation is running out of gas. Simulation will continue to be the preferred method for confirming the design meets specified intent, but simulation alone is insufficient for eliminating implementation bugs in complex designs. Just as static timing verification and equivalence checking has replaced full-timing, gate-level simulation, a combination of assertions and formal verification will replace simulation-based, ad hoc methods for finding bugs.""

Curt Widdoes, co-founder and CTO of 0-In Design Automation