SANTA CLARA, Calif.--Intel Corp. today (February 1, 2004) officially rolled out its long-awaited, 90-nm "Prescott" line of microprocessors, with plans to extend the chip to 4-GHz by year's end.

The Santa Clara-based company is also readying a new chip set that is optimized for the "Prescott" processor line, dubbed Grantsdale or i875P. The core-logic device will support DDR-400 SDRAMs, the PCI Express bus interconnect technology and its next-generation audio standard for both PCs and consumer electronics devices. The so-called Azalia specification aims to replace both AC '97 codecs in PCs and I2S codecs used in DVD players and other consumer systems. The Grantsdale chip set will begin shipping in the second quarter of 2004.

Meanwhile, as expected, Intel is shipping "Prescott," which is a 90-nm version of its Pentium 4 processor line--build on 300-mm wafers. "Prescott" incorporates a 800-MHz front-side bus and consists of its multi-tasking scheme, dubbed Hyper-Threading Technology.

The entry-level, 2.8-GHz processor comes with 1-MB of cache and sells for $178. The 3.0-GHz chip comes with 1-MB of cache and sells for $218. The 3.2-GHz processor comes with 1-MB of cache and sells for $278. The high-end, 3.4-GHz chip comes with 1-MB of cache and sells for $417.

Intel has big plans for "Prescott." "The ramp (for "Prescott") will be the fastest in the company's history," said Bill Siu, vice president and general manager of Intel's Desktop Platforms Group. "By the end of the year, we expect to hit 4-GHz (with "Prescott")," Siu said in a conference call last week.

The processors are based on Intel's 90-nm process using 300-mm wafers. This process combines strained-silicon, copper interconnects, and a low-k dielectric material, reportedly from Intel's key supplier--ASM International B.V., according to sources. ASMI's low-k material is called Aurora.

ASMI's is also reportedly Intel's strained-silicon supplier; the chip maker is using the Dutch company's epitaxial reactors for the technology, according to sources.

The processor itself is a 125-million transistor device, with a die size of 112-sq.-mm. The seven-metal-layer architecture boasts a 31-stage pipeline. In comparison, the company's 130-nm processors are 55-million-transistor devices, with a die size of 132-sq.-mm, according to Intel. The 130-nm parts feature a 20-stage design and a six-layer-metal process, according to Intel.

With "Prescott," Intel also doubled the size of L2 cache and L1 cache and improved the hardware prefetcher "to better anticipate the data need of applications," according to the company. "This helps to avoid processor stalls due to slow memory access," the company said.

The chip also boasts an improved branch predictor and integer multiplication unit. The improved branch predictor enhances productivity applications "by keeping the execution units busy," according to Intel. "(A) new integer multiplication unit improves latency and helps computational 'kernels' such as encryption and decryption. Fast shift/rotate feature also helps computational kernels such as encryption and decryption," according to Intel.

It also includes other features, such as store buffers. This enhances performance "by allowing the processor to continue executing instructions without having to wait until a write-to-memory and/or cache is complete," the company said. "Eight write-combining buffers (compared to six in the previous generation) help many applications by allowing multiple writes to be assembled and written further out in the cache hierarchy as a unit, saving port and bus traffic," the company added.

''Four entries added to the floating point schedulers to enhance floating point and media application performance, especially in HT Technology configurations," according to Intel.