Instead, Intel (Santa Clara, Calif.) plans to extend its existing and conventional 193-nm wavelength “dry” scanners for use in processing the critical layers at the 45-nm node, said Mark Bohr, senior fellow and director of process architecture and integration at the microprocessor giant.

“That is the plan for our standard technology,” Bohr said. “Immersion is still an option that we’re looking at for 32-nm,” he added.

Intel made the disclosure amid Wednesday’s introduction of the company’s 45-nm process technology. Intel’s disclosure raises questions about the viability of 193-nm immersion lithography, a technology being introduced to overcome supposed limitations with dry lithography. Immersion has been touted as the way to produce chips at the 45-nm node and beyond, especially in the absence of an alternative to optical lithography, such as extreme ultraviolet lithography (EUVL).

Chip and tool makers claim that immersion is nearly ready for production, but the jury is still out on the new but unproven technology. On the other hand, many chip makers are moving full speed ahead with immersion.

Two silicon foundry providers, IBM Corp. and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), have been the most vocal about the need to adopt immersion for future IC production. Many others have inserted immersion on their lithography roadmaps, including Advanced Micro Devices, Chartered, Samsung and others.

In contrast, Intel, the world’s largest buyer of capital equipment, is currently using 193-nm “dry” scanners for both the 90- and 65-nm nodes. For its leading-edge logic devices, the chip giant mainly uses workhorse 193-nm “dry” scanners from Japan’s Nikon Corp., sources said.

ASML Holding NV also has a large installed base within Intel, but that company’s tools are mainly used for flash-memory production and the non-critical logic layers, according to sources.

Many had speculated that Intel would move to 193-nm immersion lithography for 45-nm chip production. Both ASML and Nikon have or will ship immersion tools to the chip giant, sources said.

Still others believe that Intel’s somewhat relaxed 45-nm transistor gate lengths do not require 193-nm immersion lithography — yet. The company reportedly can push 193-nm “dry” tools to the 45-nm node — with the help of phase-shift photomasks and various lithography tricks.

After the 45-nm node, Intel has publicly stated that it would like to deploy EUVL at 32-nm — if the technology can be made ready for production fabs. Some speculate that EUV could be delayed or pushed out, however. Which is one reason why Intel could be looking at immersion for the 32-nm node, analysts speculated.