Ben Sander, a principal member of technical staff at AMD, described Barcelona, the company's first 65-nm server chip and its first native quad-core architecture at a presentation at the Fall Processor Forum here Tuesday (Oct. 10). Improvements range from 128-bit wide multimedia pathways to an upgraded memory controller and a third-level cache.

"A lot of these enhancements involve just a few percentage points of added performance here and there in an effort to build up a story about significant improvements to the overall architecture," Sander said.

AMD will not detail until later this year expected benchmarks for its quad-core processor.

Barcelona widens from 64- to 128-bits the width of the execution path for multimedia instruction extensions. In tandem, the chip speeds up the rate at which it feeds multimedia data and instructions to the CPU. The moves will give a boost to a range of media encode/decode and technical computing applications.

In addition, the company has redesigned the two memory controllers on the Opteron so they can act independently. That should make more DRAM banks available at any given time and reduce page conflicts, Sander said.

The updated memory controller will support DDR2, DDR3 and fully buffered DIMM memories. However, AMD does not expect OEMs to use the first generation of FB-DIMMs with Barcelona, Sander said.

Barcelona provides two levels of private cache for each core, a 64Kbyte L1 and 512 Kbyte L2. The chip sports a relatively small 2Mbyte third-level cache that will be expanded in a follow on CPU.

To speed up virtualization, Barcelona builds in hardware support for nested paging. The feature essentially caches address translations to reduce memory accesses that take up as much as three-quarters of the time of today's virtualization software.

"We have achieved a 20:1 server consolidation ratio inside AMD using virtualization, so it's obviously a huge cost savings," said Sander.