Alex Solomatnikov, a researcher at Stanford University detailed a chip multiprocessor generator as a flexible, universal computing platform "that will supersede the microprocessor." Under the scheme, designers would first configure and program a flexible computing framework to run applications with the desired performance. The system would then compile the program and configuration, tailoring the original framework to create a chip optimized for a desired set of applications. "Thus, the user gets the reduced development costs of using a flexible solution with the efficiency of a custom chip," said Solomatnikov.

Solomatnikov acknowledged that many issues must be addressed before such a system could be designed. One is the requirement for an automated backend toolset that could use the finished logic to create a chip with little manual intervention.

Stephen Edwards, a researcher at Columbia University, made the case for a "precision timed" (PRET) machine. "Current architectures strive for superior average-case performance that regrettably ignores predictability and repeatability of timing properties," according to Edwards. "C says nothing about timing, so timing is not considered part of correctness."

Edwards cited avionics applications as an example: In "fly-by-wire" aircraft, where software interprets pilot commands and transmits them to actuators through networks, software certification is extremely expensive. Moreover, the entire system must be certified, not just the software. "If a manufacturer expects to produce a plane for 50 years, it needs a 50-year stockpile of fly-by-wire components that are all made from the same mask set on the same production line," said Edwards.

He called for a new era of processors with temporal behavior controlled as easily as logical functions. The proposed PRET machine would seek to provide networked, real-time software delivering the reliability and timing precision of synchronous digital hardware with the simplicity of software.

"Timing precision is easy to achieve if you are willing to forgo performance; the engineering challenge in PRET machines is to deliver both. While we cannot abandon structures such as caches and pipelines and 40 years of progress in programming languages, compilers, operating systems and networking, many will have to be rethought," Edwards argued.

Farinaz Koushanfar, a researcher at Rice University, proposed using EDA tools to integrate unique identification keys into gate-level ciruits as security protocols. "In the near future, the key design dilemma will be providing security solutions that would cover all aspects of the design—from design reuse methodology, to architecture and to implementation," said Koushanfar.

In current silicon technology, she claimed the number of manufacturing process variations across different ICs made from the same mask and design is sufficient for unique characterization of each IC with high signal-to-noise ratios. Secure IDs could be used to produce software that can only run on a specific IC, thereby preventing software piracy.

Finally, Blaze DFM Inc. researcher Puneet Gupta claimed that simulations show that line-end shortening (LES), which is considered a catastrophic failure in circuits, isn't all bad. LES is caused by imperfections in lithographic printing when polysilicon gates in MOS devices exhibit ciruit shorts. Gupta claimed that under most circuit conditions, LES does not catastrophically affect circuit functionality. Simple canonical circuits used to assess the impact of LES on performance showed that it leads to faster devices.

"We are currently pursuing further investigations of the LES phenomena and tying the results up into a design-aware smart lithography rule checker," said Gupta.