LONDON — Tilera Corp. (Santa Clara, Calif.) has said it has started shipping its Tile64 processor, a 64-processor chip based on an architecture that could scale to hundreds and even thousands of cores, according to the company.
The company claimed in a statement that the processor, which is able to run multiple instances of the Linux operating system, delivers 10X the performance and 30X the performance-per-watt of the Intel dual-core Xeon, and 40X the performance of the leading digital signal processor from Texas Instruments Inc. Initial markets for the Tile64 include embedded networking and digital multimedia processing, the company said.
The Tile64 contains its processors in an 8 by 8 grid with each one capable of between 600 and 900-MHz clock frequency while consuming between 170 and 300 milliwatts per core. Idle tiles can be put into low-power sleep mode, the company said.
The chip is implemented in a 90-nm CMOS manufacturing process and processors handle 32-bit data, and smaller word sizes, according to a Tilera spokesperson. Overall the chip can provide up to 192 billion 32-bit operations per second or 3-BOPS per processor, Tilera stated.
Tilera was founded in 2004 to bring to market the research of Anant Agarwal, who has researched mesh-based multicore architectures since 1996. Agarwal, professor of engineering and computer science at the Massachusetts Institute of Technology, serves as chief technology officer of Tilera and Devesh Garg, a partner at venture capital company Bessemer, serves as chief executive officer. Tilera was admitted to the Silicon 60, EE Times' list of 60 emerging startup companies, in version 6.0 published in June 2007
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