SAN JOSE, Calif. – CEVA today announced second-generation DSP subsystems for its CEVA-X DSP cores. The CEVA XS-1100A and XS-1200A subsystems target wireless baseband and multimedia applications, respectively. The company claims a 10% higher clock frequency over previous generations, 20% smaller area (600k gates for the CEVA-XS1200A + CEVA-X1622 DSP core), 20% lower leakage power, and 10% lower dynamic power.
The wireless baseband optimized XS-1100A tightly couples the DSP to a CPU through synchronous bridges. This ensures that the XS-1100A can meet the tight real-time requirements of baseband processing. There are two single channel DMAs and no TDM ports, reflecting the fact that in baseband applications data transfers are typically handled solely by the CPU.
(Click to enlarge)
Figure 1. CEVA XS-1200A high-level block diagram
In the XS-1200A (Figure 1), there are asynchronous bridges, allowing for a decoupled system. This allows the XS-1200A to manage the multiple independent clock systems often encountered in multimedia SoCs. The platform provides 4 TDM ports for audio and video data. There are 16 DMA channels that support "3D" DMA transfers. The third dimension refers to the DMA's ability to fetch data and arrange it intelligently in memory for more efficient processing by the DSP. For instance, when processing a frame of RGB video, the DMA engine could grab sequential 8x8 blocks, arrange them conveniently in memory, and handle loading new frames. The XS-1200A also features an accelerator interface, easing the offloading of processor intensive tasks such as 3D graphics.
Power gains have been achieved through a variety of techniques, including: clock gating for all peripherals as well as each execution unit within the DSP (multiplier, AGU, etc.), smart toggling of the interconnect matrix (AHB Matrix), the ability of the CPU to externally shut down/wake up the DSP, and software controlled frequency scaling. The cache memory system in both platforms also reduces power by reducing external memory accesses.
Another notable feature of both platforms is the code replacement unit (CRU). This allows for bug fixes in hardwired ROM. If a bug is found after the silicon has spun (an all too common problem), designers can use the CRU to write new code to an unused ROM address. The CRU then creates a branch instruction that instructs the processor to bypass the buggy code.
For more information, visit http://www.ceva-dsp.com/
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