BEAVERTON, Ore. — The world's first 3-D chip process is ready for licensing from the fabless semiconductor design house BeSang Inc.

BeSang fabricated demonstration chips with 128 million vertical transistors for memory bit cells above their control logic. The chips were designed at the National Nanofab Center (Daejeon, South Korea) and Stanford Nanofab (Palo Alto, Calif.). BeSang said its process, which is protected by over 25 patent applications, will allow flash, DRAM and SRAM to be placed atop logic, microprocessor cores and SoCs.

BeSang claims it achieved 3-D by fabricating logic circuitry using a high-temperature process on the bottom and by fabricating memory circuitry using a low-temperature process on top of the logic. By placing logic and memory on different layers of the same 3-D chip, BeSang's process packs in more die per wafer, which translates into lower costs per die.

"BeSang was founded five years ago to work on 3-D IC technology," said Sang-Yun Lee, BeSang's founder and CEO. BeSang "has introduced a single-chip 3-D IC process that is ready for commercialization. By using a low-temperature process and orienting vertical memory devices on top of logic devices, we make more dies per wafer, and that is how the cost per die goes down."

At BeSang ("flying high" in Korean) Lee perfected the first true 3-D IC process with former Samsung engineer Junil Park, developer of the first atomic layer deposition tool for high-k dielectrics. Because the new IC processing technique does not stack dies, the company claims normal cooling techniques will work, for no additional heat is generated by its slightly thicker 3-D chips.

Current planar (2-D) chips that contain memory must surround their memory arrays with logic circuitry to address bits and to perform logic functions. Placing memory and logic alongside each other forces the use of long interconnection lines between the two.

BeSang, on the other hand, placed logic circuitry on the bottom layer and the memory bit cells on the higher layers of the 3-D chip, enabling very compact designs with very short interconnection lines between them.

Prior to BeSang's deisgn, "all the previous attempts were pseudo 3-D," said Simon Sze, who co-invented the floating-gate transistor for nonvolatile memory cells in 1967 at Bell Labs. Sze is now a professor at the National Chiao Tung University in Taiwan.