SAN JOSE, Calif. -- At the upcoming 2008 IEEE International Electron Devices Meeting (IEDM), Intel Corp. is expected to take the wraps off its new 32-nm process technology for high-performance microprocessors.
According to the IEDM paper, Intel built a functional 32-nm, 291-Mbit SRAM array test chip with a 0.171-micron2 cell size. The device has nearly 2 billion transistors, and an array density of 4.2-Mbit2.
The test chip operated at 3.8-GHz at 1.1 Volt, according to the paper. Intel (Santa Clara, Calif.) is expected to deploy its first immersion lithography scanners at 32-nm. The 193-nm machines will be sourced from Nikon Corp. (Tokyo).
The process also makes use of a second-generation, high-k/metal gate technology, a strained channel, and nine levels of low-k interconnect dielectrics, according to a sneak preview of the paper.
The process enables the highest drive currents reported to date for 32-nm technology. NMOS saturated drive current is 1.55-mAmicron while the corresponding PMOS value is 1.21-mAmicron.
At IEDM, there are also other major papers. HRL Laboratories will describe the integration of RF CMOS and indium phosphide (InP) transistors.
''Indium phosphide (InP) transistors are much faster than those made from silicon, but dense InP integrated circuits haven't been made because indium phosphide technology is less advanced and harder to work with than silicon, and it costs much more,'' according to the paper.
HRL is said to have integrated entire wafers of high-performance 250-nm, 300-GHz ft/fmax InP DHBTs (double-heterostructure bipolar transistors) with wafers of IBM's existing 130-nm RF-CMOS technology, according to the paper.
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