SAN FRANCISCO -- At this week's International Electron Devices Meeting (IEDM) here, IBM Corp. will provide a sneak preview of its MRAM, based on spin torque transfer (STT) technology.
In a paper, IBM will describe the key element of a 4-Kbit test device. The element, dubbed a magnetic tunnel junction (MTJ), is a 70- x 210-nm2 device said to have 10-year data retention cycle, a breakdown-to-voltage margin over 0.5-V and a read-induced disturbance rate of 10-9.
An 8-Ohm um2 MTJ is said to show ''sufficient'' read/write margin, thermal stability and write endurance. The device is said to be free of unwanted write-induced magnetic reversal.
The technology could enable a 64-megabit device based on 90-nm design rules, according to IBM's paper. IBM builds MTJs with MgO tunnel barriers. With those design rules, a single-bit line can be as tiny as 9F2.
''For the targeted MTJ operating point at (about) 4 x 106 A/cm2, the cell size is 30F2,'' according to IBM.
Last year, IBM launched a joint research and development project with TDK Corp. to create high-density magnetic random access memories (MRAMs). The new multiyear program will aim for a 20-fold increase in the memory density of MRAMs by switching to a writing mechanism, called spin-momentum transfer, that draws less power and uses smaller bit cells.
STT-based MRAM is gaining steam in the market. Korea's Hynix Semiconductor Inc. and Japan's Renesas Technology Corp. have separately announced deals for Grandis Inc.'s technology. Japan's Toshiba Corp. and Korea's Samsung Electronics Co. Ltd. are reportedly taking a close look at Grandis' technology.
IBM, Everspin and others are reportedly devising at their own STT technologies. Most MRAMs write data by applying the magnetic field generated by a current running through a wire near a tunneling magnetoresistive (TMR) element to change the magnetization. That enables fast operation but gobbles up power.
Grandis' spin-torque transfer method uses a spin-polarized current to switch magnetic bits, a technique that is said to consume less power and enhances scalability. An STT-RAM writes data by aligning the spin direction of the electrons flowing through a TMR element.
All told, STT-RAM claims to combine the capacity and cost benefits of DRAM, the fast read and write performance of SRAM, and the non-volatility of flash.
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