SCOTTSDALE, Ariz.—CebaTech Tuesday (March 10) launched its first IP products—a library of tunable silicon IP cores targeted at system-on-chip (SoC), ASIC and FPGA designs.
According to CebaTech (Eatontown, N.J.), the first four members of the CebaRIP library implement standard data encryption and compression algorithms used in storage, storage area network, network-attached storage and network applications. CebaRIP cores can be tuned for reuse in multiple application scenarios, each with different application-specific performance, power, area and cost requirements, the company said.
Multiple disparate cores can be configured in a plug-and-play ensemble to boost performance and provide a system-level solution, CebaTech said.
CebaRIP cores utilize CebaTech's high-level synthesis flow, based on the company's C2R Compiler, to meet customer-specific application requirements, CebaTech said. The company also develops tunable cores that implement customers' proprietary algorithms.
"Data management IP cores such as compression, encryption, deduplication and so on, are the natural first step in our CebaRIP core roadmap," said Ramana Jampala, CebaTech CEO, in a statement.
The first four cores in the library consist of a data encryption core, two data compression cores and a data decompression core. All cores are available now and use a stream interface or a PCI interface, according to the company.
CebaRIP cores are delivered as synthesizable Verilog RTL source code, accompanied by a simulation environment and scripts and a user's guide, the company said.
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