''With the chip industry staying on Moore's Law and lithography stuck at the 193-nm wavelength, chip makers are looking to double patterning to drive linewidth shrinks,'' said C.J. Muse, an analyst with Barclays Capital, in a report.

In doubling patterning, an IC maker is essentially doubling the process steps and creating two masks, thereby boosting production costs. Double patterning can be implemented in three ways: litho-etch-litho-etch, litho-freeze-litho-etch, and the sidewall spacer approach, also called SADP.

''SADP is the technology of choice in NAND, with all players adopting SADP at the 32-nm node,'' Muse said. ''In our view, SADP was really the only choice due to (i) inadequate overlay and line edge roughness capabilities of the then existing litho tools, (ii) the simple nature of NAND 1-D structure, and (iii) availability of excess etch and CVD tool capacity.''

Going beyond 32-nm, SADP still has an edge. ''Looking to the 22-nm node, our checks suggest that SADP is the preferred option for all the major NAND manufacturers as development is already underway and litho tools by themselves alone are not yet ready to satisfy the requirements at 22-nm,'' Muse said.

''At 22nm, it appears currently that SADP might be required for three layers--STI, gate and bit line-- instead of only one layer at 32-nm,'' the analyst said. ''And that would be expensive. This will likely prompt redesigns/workarounds of the NAND architecture and the process flow which might ultimately reduce the number of layers for which SADP needs to be adopted, at least at the manufacturers that are cash strapped. Another variable is that breakthroughs in EUV might insert EUV sooner than expected.''

And what about DRAM? ''But the story changes a bit for DRAM. DRAM offers a more complicated 2-D structure and has 3x as many critical layers at the 4x node and 9x at the 3x node-- thus driving the cost of SADP that much higher,'' the analyst said. ''This said, SADP is a proven technology and SADP is at least currently the "roadmap entry" for most DRAM makers for the 3x nm node.''