Even as suppliers ramp up double-data-rate SDRAM this summer, manufacturers say new techniques will quickly supplant the 2.1-Gbyte/s bandwidth of their PC2100 DDR modules with PC2600 devices able to deliver throughput of 2.6 Gbytes/s. By year's end, that speed could increase to 3.2 Gbytes/s, although volumes will likely be limited, according to observers.

The performance of a single-DIMM PC3200 will equal that of two dual-channel Direct Rambus RIMM modules, said Bob Goodman, chief executive of Kentron Technologies Inc., a Wilmington, Mass., DDR-module vendor. "And DDR doesn't stop there," Goodman said. "We expect to get modules up to twice as fast-as much as 6.4 Gbytes/s."

"The beauty of all this is that the DDR die doesn't change," said Desi Rhoden, president of Advanced Memory International Inc. (AMII), a San Jose-based industry group promoting the DDR interface. "All the speed increases are accomplished using the same DDR chip coming on the market now," he added.

The DDR interface features a number of options to boost performance, such as the ability to reach new speed grades by refining production of the basic DDR die. "We can squeeze another speed rate out of DDR to PC2600 just as we did with PC100 going to PC133. That will be a matter of development for the second half of this year," said Mike Seibert, DRAM strategic marketing manager at Micron Technology Inc. of Boise, Idaho, during a recent industry conference.

Taiwan's Via Technologies Inc. will start producing DDR-enabled chip sets for PC1600 and PC2100 modules this fall, but is planning new versions to support PC2600 modules expected later this year or early in 2001, said Eric Chang, marketing manager at Via. The company is also developing a motherboard that will use a FET-switch IC to boost existing PC1600 and PC2100 modules to 2.6 Gbytes/s or more, he said.

Kentron Technologies expects to sample a DDR module with a FET switch in September that will double the speed of an existing PC1600 module to 3.2 Gbytes/s. The FET basically doubles DDR SDRAM speed by cutting the typical 5-ns memory-clock cycle time in half, said Chris Karabatsos, the company's president and chief technology officer.

"The FET closes one side of the [DDR] DIMM module while opening the other side" during either the rising edge or falling edge of the clock, Karabatsos said. This enables data-transfer rates of 2.5 ns, essentially doubling performance again.

Kentron's Goodman said the technique, called Quad Band Memory (QBM), requires a slight modification to DDR chip sets and motherboards. Kentron is organizing a QBM alliance composed of semiconductor makers, motherboard vendors, and OEMs to develop the infrastructure for the new FET-based DDR approach.

A new chip-scale ball-grid-array package is in preliminary testing to further speed PC1600 performance. A JEDEC subpanel next week will be briefed on the progress of the new DDR package. JEDEC is said to be targeting an industry spec early next year for the new package, which uses the existing DDR die.

The industry's move to chip-scale packaging is becoming necessary as memory speeds require producers to adopt leadless packages to cut impedance and inductance, which slow memory cycle times.

The DDR packaging effort parallels the move already taken by Direct Rambus DRAM, which uses micro-BGA packaging technology developed by Tessera Inc. in San Jose.

In addition to DDR chips, memory suppliers are developing quad-data-rate SDRAMs, squeezing four operations into a single clock cycle using the existing DDR architecture. Sources said the bulk of the quad-speed operations will be handled by the chip set and motherboard BIOS.

QDR chips in a CSP package using a FET-switched module could potentially achieve fantastic speeds -- up to 6.4 Gbytes/s, according to industry executives. Sources said it will likely take a year or more to develop QDR SDRAM prototypes. The DDR speed boosters are considered interim upgrades and ultimately will be succeeded by DDR-2, the next big memory architectural change, which is expected sometime in 2003.