In fact, AMD claims that its pioneering ramp-up of copper processing and silicon-on-insulator (SOI) wafers at its Fab 30 here will benefit archrival Intel, which can now get mature and lower cost equipment as it moves into the new technologies.

The Dresden fab has been processing all its wafers with copper interconnects from the start of production in late 1999. It is now starting to process SOI wafers and by 2H '02 will be exclusively with SOI to make the new Claw Hammer and later Sledge Hammer 64-bit processors.

At the same time, Hans-Raimond Deppe, AMD vice president and general manager of AMD Saxony Manufacturing, conceded that his firm will benefit similarly by Intel's spearheading 300-mm wafer fab development. "When AMD starts its first 300-mm wafer production in 2005 we will benefit from all the work Intel and others have done working with tool makers to perfect their equipment," he added.

But Deppe maintained that there is no quid-pro-quo in benefits, since he said AMD's much smaller processor die size doesn't force the firm to rush into 300-mm wafer production as rapidly as Intel. "The very large Pentium 4 and Itanium die size means Intel has to go to 300-mm wafers to cut costs by getting more die on a wafer. By contrast, AMD can scale down our die size using next generation 0.13-micron processing and later 0.09-micron processing to stay ahead of Intel in die size."

The AMD executive claimed that the Dresden fab's 5K wafer starts a week all using copper interconnect is one of industry's largest uses of copper. AMD Fab 30 has totally eliminated aluminum interconnects, using tungsten on two chip local interconnect layers.

The plant chieftain said AMD "took great risks in bringing up Fab 30 in late 1999) exclusively with copper. "The tools were not mature, and we had to work very closely with equipment makers to iron out all the bugs. Every time we added new equipment we needed tool-to-tool matching. As we ramped up from several hundred wafers a week to a few thousand a week, you would discover new problems that had to be worked out."

He believed rival Intel Corp. is undergoing the same learning curve as that firm now ramps up its copper processing in more and more fabs. "But they get a mature tool set, thanks to all the work AMD and other copper pioneers did. And because of the equipment firms' larger economy of scales, the tools are less costly than we had to pay," he added.

AMD's move next year into SOI wafers -- again reaching 100% in the second half -- will score a jump over its chief MPU competitor, which has yet to put SOI on its manufacturing roadmap. Deppe said SOI increases processor performance at high speeds by curtailing multicapacitance of transistors on the chip.

SOI is not the manufacturing challenge posed by copper, since AMD buys its SOI wafer blanks already fabricated by Soitec, he explained. "Still you have to design the processor circuitry differently for SOI. All the CMOS rules for transistor interaction on the chip change to take full advantage of SOI," the fab executive asserted.

The Dresden fab is starting limited production now on 0.13-micron processing, and by 2H '02 will be 100% at this technology, the AMD executive said.

He felt Fab 30 was transitioning well to 0.13-micron using phase shift masks with the existing ASML 248-nanometer exposure tools that were installed from the beginning of the plant. "In fact, we are hoping we can get to 0.09-micron (processing) using phase shift masks with our current lithography tools," he added.

AMD has no target date when new 157-nm wavelength lithography tools would be introduced into Dresden. If the present exposure tools can be extended to 0.09-micron processing using phase shift masks, then perhaps only test equipment at 193-nm might be installed. Deppe said AMD hopes 193-nm lithography using phase shift masks could then be extended to 0.06-micron processing

"That would mean we could skip 157-nm tools entirely, which have been targeted for 0.07 and 0.06-micron (processing)," he added. Like most technologists, Deppe also believes Extreme Ultraviolet (EUV) Next Generation Lithography will be needed for the 0.045-micron semiconductor node.