In one of two ISSCC papers, Rambus engineers described a 2.2-Gbyte/sec. signaling interface for main memory that uses a delay-lock loop (DLL) to enable in-system timing calibration with 1.4-degree resolution and output drivers with limited positive feedback to increase voltage margin. This signaling interface has been used to produce prototype chips operating up to 2.6-Gbyte/sec. in standard chip-scale packages (CSPs), according to Rambus.

A second ISSCC paper described a 25% increase in bandwidth from the company's Quad Rambus Signaling Level (QRSL) signaling technology. The new technology pushes QRSL to a transfer rate of 2 Gigabits per second per pin. This technology has been tested in systems representing low-cost consumer products, said the company.