The NAND flash market is currently being served by a one-size-fits-all solution. This requires a trade off between density and performance in order to minimize costs. Vendors try to achieve both goals in order to serve the entire market space, but ultimately must focus on one aspect.

This article will compare three different flash vendors in Samsung, Toshiba, and Renesas, compare the different strategies of each, and provide a Semiconductor Insights expert view of which approach we expect to succeed in the long term.

As mentioned, the two different optimization schemes are density and performance. As applications grow in complexity, the amount of memory necessary to store the functionality grows as well. This leads to a need for larger memory sizes. Greater performance is achieved through programming bandwidth and access times. These attributes allow for faster running applications, providing superior information exchanges.

In order for a company to compete in a one-size-fits-all market, they use a mix of process technologies, process types -- single bit per cell (SBC) or multi level cell (MLC), memory technologies -- NAND or AND, and other innovations in circuit design to optimize programming bandwidth, increase density and reduce die size, thus lowering costs.

The table below provides technical information on memory devices from Samsung, Toshiba, and Renesas.

Samsung chose to follow a performance scheme. The device uses single bit per cell technology to produce a high performance product. They are, however, able to maintaining a high density by using a more advanced process technology in an effort to decrease die size. Overall this results in a memory device with very fast programming and access times while still achieving a very competitive Mb/mm² capacity.

Toshiba achieves an advantage by opting to pursue a capacity scheme. When comparing the two devices, it may be noticed that they both have 2-Gb densities. The differentiating factor is that the Toshiba is using multi level cell and a larger process technology to achieve the same density. As Toshiba focused on capacity, they achieve only moderate performance.

Renesas has announced the release of a device that claims to achieve top performance, the highest density and the lowest cell size using an advanced process technology. Unlike Toshiba and Samsung, Renesas is trying to focus on both the performance and density schemes.

Analysis of scaling cell size

Semiconductor Insights has performed extensive analyses on both the Samsung and Toshiba memory devices, including memory cell size measurements. The smaller the cell size, the less amount of die space the cell will take, enabling a smaller amount of wafer usage and lowering costs.

The Samsung device, by means of a 90-nm process technology, had a physical cell size of 0.0398-micron². Samsung has produced a single transistor flash cell measuring only 0.185-micron² by 0.215-micron². This is the smallest cell size that SI has measured in the NAND flash market as of Q4 2004.

The Toshiba device, implementing a 130-nm process technology, has a physical cell size of 0.070-micron². While the Samsung physical cell size is almost half the size of Toshiba's, both devices end up with the same logical density due to the Toshiba's use of MLC technology. Effectively, the logical cell size of the Toshiba device in 130-nm process ends up being half of the physical cell size, or 0.035-micron².

SI has yet to analyze the Renesas 4-Gb flash, which has just been released for sampling. We strongly believe that the stated cell size of 0.016-micron² provided in the Renesas announcement is the logical cell size, not the physical cell size. As seen with the Toshiba memory device, this results in a physical cell size twice that of the logical cell size, or 0.032-micron² in this case; which is within the range of expected cell sizes in 90-nm process technology.

Assuming that the claims in the Renesas announcement are accurate when implemented, SI anticipates that the die size for the 4-Gb memory device should be in the range of 130-mm² based on the 0.032-micron² cell size and industry standard metrics for peripheral circuitry.

Optimizing cell size is key to reducing cost structure. Peripheral circuits add only a small percentage to the overall die cost structure. For example, in the Samsung device the total area occupied by the memory array and peripherals (including wordline drivers, bitlines and sense amplifiers) is 114.8-mm² out of a total of 144-mm². This represents approximately 79.7% of the chip. For the Toshiba part, the memory array and peripherals occupy 122.39-mm², representing 81.67%ïof the die.

The aggressive scaling of the flash memory cell will continue to be the major driver in data storage markets. Vendors such as Toshiba and Renesas may be able to logically scale the cell size through MLC technology, but this makes the higher density products unattractive to performance-oriented markets

NAND flash programming performance

Due to the more complex sensing circuitry required for MLC implementation, SBC devices have typically posted superior programming performance. This is seen in the devices we analyzed. Following the performance scheme, Samsung is the market leader, providing >6 MB/s programming bandwidth. Toshiba, being more focused on density than performance, uses MLC technology providing a considerable bandwidth performance lag of 1-1.5 MB/s.

Renesas is planning to offer a unique block management approach that will allow it to simultaneously program 4 blocks. In reality the programming bandwidth is approximately 3.5 MB/s, meeting the expectations for a MLC device in a 90-nm process technology, but due to the innovative concept, the bandwidth performance will be effectively elevated to 10 MB/s. This innovation might provide a reasonable work-around to their inherent MLC performance issue.

We expect to analyze the circuitry in the Renesas device and any accompanying controller circuitry required to support the simultaneous 4 block programming before fully endorsing this solution at the flash Card "system level". For the moment, we believe that for performance markets, using leading process technology coupled with SBC circuitry is a more reliable and achievable solution.

In conclusion, SI believes that the NAND flash memory market is reaching a critical size. Given this, the best approach will be to provide a solution for both the density and performance markets, rather than a one-size-fits-all solution. The additional performance or density not required in an application will increase the cost of the system, which is not desirable for the OEM.

The recent drop in ASPs reflects the fact that the NAND Flash market is maturing. Toshiba and Samsung are changing their strategy by segmenting the market into density and performance. Samsung has recognized the density superiority of MLC solutions and recently announced its plan to introduce higher density MLC-based NAND flash products. Toshiba has likewise released information about a high performance SBC product utilizing a 90-nm process technology.

Renesas is hoping to be successful with the strategy that market leaders Samsung and Toshiba had been using by trying to provide a device that will suit the entire memory market. We believe that the growth of the NAND market will probably reward the segmentation approach that Toshiba and Samsung are introducing.