TOKYO — Seeking to break the limitations of producing complex ICs on present processes, a startup here plans to stack chips atop one another to create 3-D circuits with advantages it claims systems-on-chip and systems-in-package can't match. ZyCube Co. Ltd. intends to commence fabrication of 3-D chips in the second half of 2005, with commercial devices expected in 2007.

ZyCube's 3-D circuits will avoid the extensive internal wiring, propagation delays and power consumption of complex systems-on-chip that integrate multiple functional blocks, the company said. ZyCube will also be able to combine silicon and compound-semiconductor dice into single devices, creating 3-D circuits that cannot be made as single-chip SoCs with present technology.

"We've developed a method to build brand-new LSIs," said professor Mitsumasa Koyanagi, a Tohoku University researcher who now is ZyCube's chief technology officer. "It's an ultimate form of LSI fabrication."

ZyCube said that its 3-D circuits will also improve upon system-in-package devices, which stack LSIs and connect them via wire bonding. ZyCube will create its circuits with a technology called Smart-Stack, which uses buried vertical vias to improve the number of connections between chips, allowing for parallel operations to improve performance. The company said its approach will shrink fabrication times and lower production costs.

Koyanagi and president Manabu Bonkohara were the main forces behind ZyCube's founding in March 2002. Bonkohara at the time was project leader of 3-D LSIs at the Association of Super-Advanced Electronics Technologies, a national R&D institute, having overseen the ASET 3-D research effort that ended in March of this year.

"ZyCube is not an extension of the ASET project; I wanted to do business in a much more advanced area of 3-D LSIs than what was done at ASET," Bonkohara said. "Thus I founded a venture company. This is a real venture company, supported by people who understand the technology and have deep pockets." He officially became president of ZyCube in March.

Koyanagi has been studying 3-D LSIs since the 1980s and is the developer of a wafer-to-wafer stacking technology, dubbed the Tohoku University Method, that has been widely used as a basis for 3-D development at ASET as well as at overseas companies and universities. The Smart-Stack approach, completed last summer, represents an evolution of the Tohoku method.

Devices based on the Smart-Stack technology employ known-good dice or wafers. Any chips or compound semiconductors, including processors, memories, sensors, analog ICs and RF chips, can be stacked and are electrically connected by vertically buried interconnections.

Stacked LSIs are already used in system-in-package configurations, but in SiPs the LSIs are wire-bonded. ZyCube says its buried-via approach has an edge over conventional SoCs and SiPs in fabrication time, number of connections available for parallel operation and thinness (as thin as several tens of nanometers).

The Smart-Stack technology features long (about 50-micron) and narrow (down to 1-micron) trenches formed in chips or wafers to be stacked and insulated with SiO2. Wiring materials (usually polysilicon) are then used to fill in the trenches so that the trenches function as buried vias.