And from all accounts, 193-nm immersion is moving full speed ahead for chip manufacturing at the 45-nm node or sooner. Foundry rivals IBM Corp. and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) have separately produced various chips with ASML's prototype 193-nm immersion scanner, while Nikon claims to have demonstrated 65-nm imaging with its lithography technology, according to papers at SPIE.

However, there are still some major challenges for immersion lithography in the market, such as polarity and fluid limitations, according to analysts. And some believe that 193-nm "wet" immersion will only become a "one-node" wonder at the 65-nm node, paving the way for next-generation technologies such as extreme ultraviolet (EUV) or maskless.

"Immersion is practical for 65-nm half-pitch," said Shinji Okazaki, director of EUV process technology research at the Association of Super-Advanced Electronics Technologies (ASET), an R&D organization based in Tokyo.

"For 45-nm half-pitch, immersion is going to be difficult," Okazaki said. "It will be expensive and difficult to use."

He said that EUV is more suited for 45-nm half-pitch design rules, which is slated for 2010 on the ITRS road map. "We will (deliver EUV) one or two years before that," he said.

Still, immersion is gathering plenty of momentum in the marketplace, while EUV remains hampered with lack of suitable sources, photomask technologies and overall costs.

At SPIE, for example, ASML of the Netherlands is expected to get separate and major endorsements from foundry competitors IBM Corp. and TSMC.

In one paper at SPIE, ASML and TSMC (Hsinchu, Taiwan) will describe one of the first chips processed with ASML's AT:1150i immersion scanner. The AT:1150i, ASML's original immersion prototype, has a relatively low numerical aperture of 0.75.

With the tool, TSMC processed an 8-megabit SRAM chip based on a 90-nm process and a 120-nm half-pitch design rule, according to the paper. "The critical poly layers were done on the prototype AT:1150i," it said. "These results reveal the readiness and the potential risks of immersion lithography in the production environment."

IBM is also expected to present a separate paper, based on its recent announcement in the arena. Recently, IBM used a Twinscan AT:1150i lithography machine from ASML installed at the Albany Nanotech campus in New York state to make examples of a 64-bit Power processor (see Dec. 2, 2004 story).

"We were able to achieve lithographic and overlay performance that exceeded product specifications while achieving a sufficiently low defect count so as to have yielding chips and modules," according to IBM's paper at SPIE.

Meanwhile, in a separate paper, Nikon (Tokyo) is expected to present details about its 193-nm immersion program. Its Engineering Evaluation Tool (EET), a system with a NA of 0.85, has shown "line and space" imaging at 65-nm, according to Nikon's paper at SPIE.

The company plans to ship its first production tool, dubbed the S609B, in the second half of 2005, according to the paper. With a refractive optics NA of greater than 1.0, the tool will be equipped with "loss-less" polarized illumination optics for 65-nm mass production, according to Nikon. The tool is said to handle 50-nm "lines and spaces" with reticle enhancement techniques (RETs).

Future models, which will use catadioptric projection optics of NA greater than 1.3, is slated for the second half of 2006, according to Nikon.

"With immersion, we believe we can go to 45-nm," said Bernie Wood, director of marketing for Nikon Corp.'s U.S. sales arm, Nikon Precision Inc. (Belmont, Calif.).

To push 193-nm immersion beyond the 45-nm node, the industry must devise higher refractive fluids, Wood said. Nikon is also working on EUV, as a "pre-production tool" is slated for delivery in 2006. A production tool is due out in 2008, he said.