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NPU vendors eye OC-768
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Linley Gwennap A year ago, most network processor (NPU) vendors didn't know the product of 192 and 4. Now, OC-768 is in vogue as not one but four companies discussed their 40-Gbit/second NPU implementations at the recent Network Processor Forum.

As usual, innovation is coming not from the large semiconductor vendors but from fabless startups. The two leaders in the 40G race are Xelerated Packet Devices and ClearSpeed Technology (formerly PixelFusion). Also, Cognigine and Lexra disclosed 10G products that they claim will scale to 40G.

The first challenge is generating the compute power required. Vendors are packing dozens of parallel processors onto a single chip. ClearSpeed's SIMD design, for example, uses hundreds of tiny 8-bit processing elements. Even a large array of processors is not enough. Most vendors are adding hardwired units to handle special functions such as table lookups and congestion management. Cognigine is the exception, relying entirely on a programmable architecture.

A more difficult challenge is the memory subsystem. For traffic management, an NPU must store each packet in memory and later transmit it, requiring a sustained 80 Gbits/s for a half-duplex OC-768 connection. This bandwidth would require at least eight RDRAM channels, mechanically unfeasible with a single chip. A subsystem using 200/400-MHz DDR SDRAM would have to be more than 300 bits wide.

Most of the vendors have pushed traffic management onto a separate chip, enabling a high-pin-count memory subsystem. For OC-192, Cognigine plans to deliver a single chip that includes traffic management, but the company has not detailed its OC-768 approach.

Perhaps the biggest challenge will be to sell these devices. OC-768 is far from the sweet spot of the NPU market; there may be only 10 to 20 design wins at this speed over the next couple of years, hardly enough to sustain several companies.

The real driver behind 40G is venture capital. With at least 26 companies now developing NPUs, VCs are looking for differentiation, and performance is always the easiest differentiator to add.

But no matter which companies win or lose, the recent announcements show that NPUs can handle OC-768. The computational problems are solvable, and the memory issues are the same as for ASICs. This should dispel the myth that NPUs can't reach high wire speeds.

Linley Gwennap is Founder and Principal Analyst of the Linley Group (www.linleygroup.com/npu).





The views and opinions expressed in this column are strictly those of the author and should not be taken as an editorial position of EE Times or any of its other editors, publications or Web sites.


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