At its developers' forum last month, Intel announced its IXP2800 network processor, featuring a powerful and flexible new architecture. This design bucks the trend in high-end NPUs, which has been toward reducing flexibility.
Many early NPUs, particularly Intel's popular IXP1200, perform most packet processing in software running on one of several packet engines. This method provides the flexibility of implementing new protocols and algorithms. When scaling NPUs from 1 to 10 Gbits/second, however, designers found it difficult to provide enough programmable horsepower. At 200 MHz, a 10-Gbit/s NPU would require at least 64 packet engines.
As a result, most high-end NPU designers have offloaded portions of the packet-processing task into fixed-function units. These on-chip coprocessors function with little software intervention.
For example, AMCC's nP7510 has just six packet engines at 330 MHz. It uses an external search engine for classification, an on-chip policing engine and an external traffic-management chip set for queuing. A packet engine executes only about 70 instructions to fully process a packet.
At the far end of this continuum lie networking ASICs like Marvell's Prestera. Such ASICs are configurable for a variety of protocols and algorithms, but are not programmable.
The IXP2800 is at the other end of this scale: Nearly all of its performance comes from its programmable engines. To solve the scalability problem, Intel custom-designed a 1.4-GHz packet engine. With 16 of them, the IXP2800 generates a whopping 22,400 Mips. This performance is necessary, however: To fully process a packet entirely in software requires roughly 700 IXP instructions, 10 times as many as in the AMCC architecture.
The advantage of Intel's approach is its flexibility. The IXP can handle not only protocols and algorithms but completely different services, such as TCP offload, that do not map well onto fixed-function coprocessors. The programmer can arrange the engines in parallel or in a software pipeline or any combination thereof.
But the IXP programmer must choose and implement the software architecture. The nP7510, in contrast, presents a simple single-processor programming model and requires far less code. The Prestera requires almost no code.
OEMs choosing an NPU must now decide whether Intel's flexible programming model is a burden or a boon.
Founder and Principal Analyst of the Linley Group, Linley Gwennap is Coauthor of "A Guide to Network Processors, Second Edition" www.linleygroup.com/npu.
http://www.eetimes.com/
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