Most chip designers thought they had bound up the cellar years ago, running scan chains through the boundaries of the major blocks on their chips. But here is the monster back again, dragging fragments of broken scan chains still looped around its scaly legs.

Test engineers were the first to spread the alarm, with cries like these (actually heard at Semicon West this year): "We are seeing chips in which the largest single cost component is tester time," or "Sooner or later we're going to get handed a literally untestable chip design."

The forces that unleashed the monster are not surprising: increasing complexity and speed. But they combine in interesting ways. For instance, "With low voltages, very high densities and new signaling techniques, old-fashioned stuck-at testing is no longer a solution," one test architect warned. "Failures these days aren't just shorts and opens-they include crosstalk, delay and skew variations and indeterminate signal voltages. These are at-speed, under-load events that conventional testers don't see."

So the monster is stalking straight toward the design department. If at-speed test strategies aren't designed into individual circuits, there is little hope of developing affordable tests later. The solution may be as simple as making sure that all memory blocks-even the small ones-have built-in self-test (BIST) and that all low-voltage signals have programmable loop-backs. Or it may be as complex as having to create at-speed BIST for state machines, data paths and mixed-signal blocks.

If the design department breaks and runs at the monster's appearance, odds are the beast will trudge right on through to the system integrator's office. The scenario goes something like this:

Design engineers fail to anticipate the difficulty of testing the chip, so they design an inadequate test strategy. Test engineers achieve almost adequate stuck-at coverage after the fact, and at least try to characterize the chips for skews and signal integrity. But the test suite runs so long and requires such expensive leading-edge testers, that it doubles the estimated manufacturing cost. Marketing makes the call, and the test suite is scaled back to a partial go/no-go scan that runs quickly on a previous-generation logic tester. And the semi-inspected chips go right on through to the OEM.

Unfortunately, this isn't science fiction anymore.