Once a marketing department latches onto a new phrase, it's hard to tell if any useful meaning is left in it. This fate has befallen a previously useful term, system-on-chip (SoC.) It has become so popular to claim that a company's latest effort is an SoC design that marketers apply the adjective to just about anything now. But somewhere under the hype lurks an important idea.
The problem is definition: When is it useful to call a design SoC? There is very little agreement within the industry. The easiest definition uses scale: If a design is big, it is SoC. You can count transistors or measure the perimeter of the die and tell whether you have an SoC or not. But this approach ignores true complexity. For instance, a 1-Gbit DRAM is huge by almost any measure, but few engineers would agree that it's an SoC design.
Another approach says that a design is SoC if it includes several different types of structures. Most frequently cited contents are at least one CPU core, peripheral cores and a couple of types of memory. Again, the test is easy: You look at a layout diagram of the die and check off the blocks. But here again there is a problem, most succinctly stated by an engineering manager with whom I spoke recently: "Gee, does that mean my 8051 is an SoC device?"
One could conceivably combine questions A and B to come up with a more complicated metric. If the die contains more than 1.5 million transistors, at least one CPU core, at least two different types of memory . . . But this is getting a little too arcane.
An altogether different approach suggests that the real issue in SoC is not what goes on the die, but what goes on in the design team. Try something like this: Does the design team include at least two groups of design engineers who can't communicate with each other? This would, for instance, make a design SoC if it had both substantial analog and substantial digital components, regardless of the die size.
The importance of this test goes beyond the levity with which it can be stated. In fact the major challenges of SoC design relate not to the sheer scale, nor even to the well-documented problems of combining cores from many sources, but to the very different design flows that somehow must be blended to produce a tested chip. For example, not only do analog, digital and software designers use different tools, but their entire design flows also can be quite different. Therein may lie the greatest challenge of SoC design.
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