Generally, the papers at IEDM have been about incremental changes in the design of DRAM cells, switching transistors and the like: the nuts and bolts that have to be redone every few process generations. Often the issue is not how to reinvent the MOS transistor but how to make better models of it, or improve its behavior at very narrow gate lengths or with different contact materials, or whatever.

This year, however, many of the papers are about physical limits. As geometries plummet toward 0.1-micron gate lengths, conventional MOS transistors cease to work well, and eventually cease to be useful. As gate oxides get thinner they cease to be reliable. This year's papers are not so much about incremental improvements as about radical changes.

Authors are discussing complete redesigns of the MOS transistor, including both radically different planar layouts and, at the extreme, abandoning planar transistors altogether in favor of vertical transistors. On the oxide front, there is a search both for new materials and for new deposition techniques, in the hope that it will be possible to create reliable oxides thin enough to allow the tiny threshold voltages that tiny transistors must have. Overall, the struggle is to create devices compatible with existing design methodology.

That battle may already be lost. Understandably, people don't want to say that in so many words, but the conversations in the hallway leave clues lying about. Many design teams, even with the most advanced tools, are finding poor correlation between simulations and silicon for the most advanced processes, forcing iterative design. Many point the finger at inaccurate device models. Circuit problems that defy conventional analysis tools-analog signal degradation, for instance-are appearing: not only as design failures but as unexplained field failures.

Lots of people are sticking their fingers in the holes in the dike. EDA vendors are inventing more point tools. Device and process designers are strug- gling to improve the reliability of models. Foundries are degrading performance specs on new libraries to levels that can be reliably achieved-even if they are lower than for previous process generations. But can they restore the ability to achieve routine first-time-working design to ordinary design teams? The answer to that question will change the industry.