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A physical predicament
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Ron WilsonIt hasn't been widely remarked, but as microprocessors, FPGAs and, eventually, ASICs move into the 0.18-micron generation, they are joining DRAMs in a rather unsettling distinction: Their finest features will be smaller than one wavelength of the light used to create them.

Phase-shift masks, DRAM designers learned, could produce large, regular arrays of features slightly smaller than the wavelength of the light source in the stepper. Another idea, optical proximity correction (OPC), added area to an individual feature in carefully calculated places. Instead of a tiny rectangle on the mask, you end up with a tiny rectangle on steroids. But it prints as an oval approximating a rectangle on the wafer.

With the combination of phase shifting and OPC, foundries are charging into 0.18-micron and beyond with existing steppers. But this leap appears to be playing havoc with physical design.

These new techniques have destroyed one of the identities upon which physical design was based. The polygon geometry (PG) plots created by the back-end tools, the features on the photomask and the features on the wafer are no longer identical. The masks, with phase-shifting plates and OPC features in place, look nothing like the original PG data. And the features on the die, after all these techniques have been applied, look less and less like the PG data.

Unfortunately, our tool chains extract their most accurate impedance data for delay, power and signal integrity measurements from the polygons. And while there is still a more or less one-to-one relationship between a polygon pattern in the design file and a set of features on the wafer, the relationship is not an identity. The PG file will have polygons. The wafer will inherit ellipses, circles, lines shaped like cartoon dog bones and so forth. Extraction based on polygons is increasingly irrelevant.

One obvious answer would be to extract data from the wafer features rather than the PG data. But current economics discourage running a test wafer before formal tapeout. Another approach, championed by Numerical Technologies Inc. (San Jose, Calif.), is to use software to simulate the actual wafer features from the doctored mask data. A third approach may be to change the level at which design teams interface to foundries. Rather than trying to fabricate any device customers throw at them, foundries may have to offer libraries of fully characterized cells, based on postfabrication measurement and existing process controls.

In any case, just as synthesis vendors were starting to add some physical-design smarts into their front-end tools, the back end will have to change too.





The views and opinions expressed in this column are strictly those of the author and should not be taken as an editorial position of EE Times or any of its other editors, publications or Web sites.


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